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  • Quantum-SI is available on Windows 2000/XP platforms (Solaris and Linux support planned for 2005).

  • SiAuditor is available on Solaris 2.7/2.8, Windows 2000/XP and Linux platforms, with x86 Linux and Solaris compute farms for HSPICE.


Product Configuration Matrix


Quantum-SI is available in a range of product configurations and options (shown in the table below). SiSoft's products represent the most advanced signal integrity solutions available!

  • The Quantum-SI 50/100 configurations provide a pre-layout environment for customers that need to do "What If" analysis to determine design constraints for printed circuit boards, cables and connectors prior to implementation. Both configurations come with a full signal integrity, static timing and SSO/coupled analysis environment. The Quantum-SI 100 configuration supports a seamless integration with HSPICE and its own internal Spice/IBIS simulator. The Quantum-SI 50 configuration does not have support for HSPICE as a simulation engine.

  • The Quantum-SI 200 configuration targets customers who need to perform single board pre-layout and post-layout analysis. It includes all of the functionality found in the 100 configuration, plus single-board post-layout verification and auto-generation of pre-layout schematics from the post-layout database.

  • The Quantum-SI 300 configuration provides a full multi-board pre-/post-layout environment and a rich feature set for the most demanding needs of seasoned signal integrity engineers. It includes all of the functionality of the lower configurations and adds support for multi-board systems, populations, variants, and crosstalk cross-probing for Allegro.

    For more information about other Quantum-SI and SiAuditor configurations, contact sales@sisoft.com.

    Note: HSPICE support is available with product configurations 100 and higher.



Integrated Signal Integrity and Timing Analysis

Quantum-SI and SiAuditor provide a truly integrated solution for signal integrity and timing analysis of complex high-speed multi-board systems.

  • Both products implement a methodology that encompasses pre-layout and post-layout simulations with rigorous waveform processing, automatically extracting waveform quality reports and interconnect delays.
  • Extracted interconnect delays are utilized by static timing analysis for both synchronous and source-synchronous designs.
  • Quantum-SI and SiAuditor provide the flexibility to perform all signal integrity and timing analysis at either the core of the chip, the pad of the I/O, or the pin of the package of both the source and target components.
Timing Analysis, Waveform Quality, and Eye Diagram Processing


Rigorous Waveform Processing


Quantum-SI and SiAuditor offer the industry's most rigorous waveform and eye diagram analysis, processing every edge of every waveform, across the entire solution space. With over 18 measurement levels, and the ability to uniquely specify both rising and falling parameters, only Quantum-SI and SiAuditor allow engineers to process the most advanced I/O structures and accurately assess the true waveform quality and timing margins in a design.



Integrated Pre-/Post-Layout Analysis for Major PCB Flows


Quantum-SI and SiAuditor use the transfer net as a common data structure to control both pre-layout and post-layout analysis. Quantum-SI and SiAuditor associate simulation conditions with the
transfer nets to allow for a common simulation state for both pre-layout and post-layout analysis. This tight integration between the pre-layout and post-layout process is unlike that found in any other tool.

Quantum-SI and SiAuditor Pre-Layout GUI


Quantum-SI and SiAuditor Post-Layout GUI


Crosstalk Analysis/Crosstalk Cross-probing on Allegro


Quantum-SI and SiAuditor offer crosstalk analysis capability for both pre-layout and post-layout analysis flows. In pre-layout, coupled simulations are automatically generated to identify simultaneous switching output (SSO) effects on timing and waveform quality. Post-layout crosstalk is extremely fast, providing very rapid screening of large multi-board databases. Crosstalk automatically generates coupling reports that can be used to easily identify the coupled segments that need to be corrected in order to make the design more robust. For Allegro flows, crosstalk errors can be automatically probed, which allows issues to be quickly identified and resolved.

Crosstalk Cross-probing with Allegro



HSPICE Integration


Quantum-SI has its own Spice/IBIS simulation engine and does not require HSPICE. However, most Quantum-SI product configurations also provide a seamless interface to the HSPICE simulation engine. SiAuditor uses HSPICE as its native simulation engine (i.e., HSPICE is required). Both product families provide seamless support for native HSPICE and HSPICE/IBIS simulation. Quantum-SI and SiAuditor automatically generate and submit appropriate Spice netlists and process the simulation results for waveform quality and interconnect delays. Both products can submit HSPICE-based simulation decks locally or to queuing systems, such as LSF, to maximize compute resource utilization.


Seamless Support of IBIS and HSPICE Models

Quantum-SI and SiAuditor support the inclusion of both HSPICE and IBIS models through an extended IBIS syntax. This allows for simulation with transistor level and behavioral (IBIS) models as well as the inclusion of any supported HSPICE element.



Multi-Giga Bit Signaling with S-Parameters


Quantum-SI and SiAuditor support multi-gigabit signaling analysis of high-speed serial data links using HSPICE S-Parameters. S-Parameters may be used with other standard modeling elements in the pre-layout analysis and post-layout verification flows. This allows engineers to take full advantage of SiSoft's enhanced product feature set, including support of coupled differential signals, extensive eye diagram processing, and support for deep stimulus patterns.



Progressive Discovery
Progressive discovery is the process of viewing results in a drill-down fashion from high-level summaries to low-level detailed reports. Analysis of high-speed systems requires simulation across a wide solution space that results in a large simulation database. Progressive Discovery greatly simplifies the process of identifying and correcting design errors by providing a method to quickly view system-level errors; track down and fix the source of the error; and to verify that the proposed implementation fixes the problem.

Progressive/Tiered Data Results Viewing



Lossy T-line/Stackup Editors
The T-Line and Stackup Editors provide an intuitive graphical interface to a built-in 2-D field solver that is included in Quantum-SI and SiAuditor. The T-Line editor is used to quickly set parameters associated with different physical implementations of lossy transmission lines and to create coupled models for pre-layout analysis. The Stackup Editor is used to create new stackup files or to edit existing files for post-layout verification. The 2-D field solver is used to automatically generate models from post-layout databases.

Lossy Transmission Line Editor with 2-D Field Solver



Stackup Editor



Built-in Spice/IBIS Simulator (Quantum-SI)
Quantum-SI includes an internal Spice/IBIS simulator that provides high performance simulation for IBIS I/O buffers. Quantum-SI also provides seamless support for HSPICE. With Quantum-SI, it's easy to switch between simulators using the "User's Preference" GUI.

User Preferences



Waveform Viewer for HSPICE and Internal Simulator
The waveform viewer is capable of reading and processing simulation files from HSPICE and the Quantum-SI simulator. The waveform viewer may be used to automatically generate eye diagrams and overlayed waveforms.


Waveform Viewer



Design Analysis Reuse
Design analysis reuse is defined as the ability to reuse design analysis environments within an implementation, across different physical implementations, and between pre-layout and post-layout analysis. Both of SiSoft's product families provide analysis reuse by utilizing a transfer net (similar to a net class).

Transfer Netlist
The transfer net is an implementation independent network description and serves as the primary data structure for Quantum-SI and SiAuditor. It is similar in concept to a net class, but includes key information about component connectivity, component transfers, operating frequency, and measurement points. The transfer net construct is the key to tight integration between pre-layout and post-layout and is instrumental for design analysis reuse.



I/O Characterization
Signal integrity and timing analysis relies heavily on the specifications provided by component vendors. The conditions for which these specifications are generated, and the actual design environment, can be significantly different. I/O characterization provides a method to quantify how an I/O cell operates across a range of frequency, voltage swing, and slew-rate that represent the actual design environment. I/O buffer characterization can determine operating limits and uncover I/O problems such as delay variation. It also provides a means to develop accurate chip specifications for system-level analysis.



Library and Data Validation
Quantum-SI and SiAuditor provide consistency checking across libraries and design inputs, including IBIS and timing models, transfer nets, and design netlists. Data is entered, checked, and stored in one place, and then shared between projects.



No Redundant Data
Quantum-SI and SiAuditor store data, such as clock frequency, in one location that is used for all analysis within a project and it can be shared between projects, eliminating redundant data. This feature saves time since the data is only changed in one place and it eliminates errors caused by manually synchronizing data in multiple sources.



Open ASCII Database
SiSoft's product databases are completely open. All input data that drives analysis and output results are in ASCII format. This feature allows users to create scripts to automatically generate data inputs for Quantum-SI and SiAuditor and to perform specialized processing on the output data results.



Pre-Layout Design Analysis Kits
Pre-layout analysis kits are included with Quantum-SI and SiAuditor. These analysis kits include models and design configurations that enable engineers to quickly perform signal integrity and timing analysis. The analysis kits can help customers shave weeks to months off of the traditional analysis cycle.

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