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HSIM^plus

HSIM^plus platform is for the comprehensive simulation and analysis of high performance analog, mixed-signal, memory, and system-on-chip designs including important post-layout effects.

Nanometer Verification
Sustained product innovation in the electronics industry starts with good ideas from smart designers, joined with the best in process and design technology. When these products offer compelling advantages over those of the competition梚n terms of functionality, performance, battery life, portability or cost梟ew markets are formed or existing ones changed, as end users rush to benefit from the product features and capabilities. Requirements for these products include higher levels of integration, incorporating complex analog and mixed-signal components, embedded memories and high performance logic on a single die, manufactured in an advanced, fine-line process.

This trend toward larger and more complex circuit designs on nanometer process geometries has created a circuit verification crisis for those designers still using traditional tools and methodologies. Verification resource requirements and run-times are increasing rapidly, and block-level verification can fail to find critical flaws in mixed-signal interfaces. Design sizes exceed the capacity limits of traditional tools, and with the need to consider detailed nanometer effects, traditional tools collapse under the huge numbers of post-layout parasitic elements being extracted. The number of designs requiring re-spins is going up, and not only is the risk of failure increasing rapidly, the cost of failure is large and getting larger. In today抯 age of nanometer designs, it is no longer enough to get to tape-out梬ith short product life-cycles, designs must ramp quickly to a high and constant chip yield in order to meet aggressive time to market goals. Engineering and mask costs can easily exceed one million dollars, while the cost to identify and correct circuit errors that escaped verification can approach the initial capital expense. These unnecessary rework costs and a potential lost opportunity cost of millions of dollars, can make the difference between business success and failure.

Verification of these complex and innovative designs requires a solution capable of handling designs of tens to hundreds of millions of transistors, combined with high throughput and high precision simulation. In addition, nanometer process geometries enforce comprehensive analysis of post-layout effects in order to reduce the risk that designs pass verification but fail when manufactured. These dynamic nanometer effects include off-state leakage current; crosstalk-induced delay and functional noise; and timing degradation due to power network voltage drop and ground bounce. Furthermore, it is necessary to ensure that the design will remain operational and within specification for the intended life of the end product. Over time, high current densities cause electro-migration of metal interconnect, resulting in early design failure. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) cause transistor parameters to vary, degrading performance as the design ages. To meet these nanometer design challenges a high capacity, high precision circuit-level verification platform is needed.

HSIM抯 Technology
HSIM incorporates four unique and proprietary technologies which deliver the breakthrough levels of simulation performance and memory efficiency required for full-chip nanometer circuit verification, while maintaining SPICE levels of precision.

• Hierarchical Circuit Database. This hierarchical approach to circuit storage efficiently represents repeated instances of the same sub-circuit and provides almost unlimited design capacity.

• Hierarchical Simulation Engine. HSIM抯 isomorphic matching technology takes advantage of any hierarchical structures present in the circuit, eliminating unnecessary simulation and accelerating performance. HSIM offers the latest simulation models including BSIM4 for MOS devices, VBIC for bipolar devices, and BSIMSOI3 for silicon-on-insulator devices.

• Nanometer Problems Solver. HSIM抯 proprietary methods for circuit representation are uniquely capable of handling circuits with inductors and coupling capacitors. By controlling the impact of these parasitics on the numerical solver, the simulation of parasitic effects causes only a minor slow down.

• Proprietary Parasitic Reduction Algorithms. HSIM抯 simulation core implements a state-of-the-art RC parasitic reduction capability. This reduction effectively reduces the huge volume of parasitic data associated with layout parasitic extraction, boosting performance for efficient post-layout simulation with a negligible loss in accuracy.

Figure 1. Pre-layout Flow chart

The HSIM^plus platform is built on the HSIM simulator to provide a fully integrated solution for nanometer IC design, including options for dynamic voltage drop analysis considering the timing impact of power net variation; reliability analysis of power and signal nets; coupling capacitance and dynamic crosstalk behavior; and MOSFET device reliability. Integrations with Cadence抯 analog design environment and various HDL simulators, as well as circuit screening complete the set of available options described below.

Figure 2. HSIM^plus

Post-Layout Acceleration Option (PLX)
The post-layout acceleration option affords significant improvements in simulation run-time and memory efficiency for full-chip simulations that use large numbers of extracted parasitic Rs and Cs. A wide variety of flat or hierarchical extraction flows are supported, in both DSPF and SPEF data formats. PLX distributes extracted parasitics (resistors, grounded capacitors and coupling capacitors) throughout the hierarchical circuit representation, inserting them into the appropriate location to maintain the pre-layout hierarchy for improved efficiency. Designer抯 productivity is enhanced during debugging and interactive circuit analysis, as familiar pre-layout node and device names are retained. With PLX, the benefits of hierarchical simulation and isomorphic matching technologies are available to designers performing full-chip post-layout verification, including those circuits where a high degree of coupling can otherwise result in degraded run-times and memory efficiency. PLX permits post-layout simulations that are otherwise impossible, and quickly delivers precise results.

Power Net Reliability Analysis Option (PWRA)
The PWRA option implements a direct-coupled methodology, enabling designers to determine the impact on circuit timing and functionality caused by dynamic power net voltage drop. In addition to determining the delay degradation induced by voltage drop, PWRA computes detailed time-varying power net voltage drop and current density values, producing information to pinpoint power net weaknesses. Industry-standard GDSII enables physical visualization in the designers?familiar layout viewing or editing environment. PWRA抯 direct-coupled methodology results in highly accurate transistor currents, guiding the designer to real power net problems.

When used in conjunction with PLX, PWRA can perform direct-coupled reliability analysis of highly regular and isomorphic hierarchical designs. These designs may contain hundreds of millions of transistors and hundreds of millions of power net resistors, in addition to signal net Rs, Cs and coupling capacitors.

Static Power Net Resistance Calculation Option (SPRES)
The SPRES option determines the resistance from each external power pin connection to every connected transistor terminal, generating text reports and files for graphical visualization. SPRES is used in conjunction with PWRA, rapidly checking to identify gross layout violations such as missing or incorrectly sized strapping or missing vias, in addition to quickly uncovering incorrect data from parasitic extraction. This static screening promptly uncovers electrical problems, and improves productivity by eliminating the need for users to complete lengthy simulations in order to analyze gross errors in power net layout.

Signal Net Reliability Analysis Option (SIGRA)
The SIGRA option calculates current densities in narrow signal nets, to determine their susceptibility to electro-migration. Bi-directional current flow is correctly considered, including calculation of the RMS currents required for monitoring Joule heating within the design. These results are presented as GDSII files for physical visualization, complementing the PWRA option. When used in conjunction with PLX, SIGRA can include all of the design抯 extracted coupling capacitors in addition to the grounded capacitors. This provides a high level of precision in determining the current entering or leaving segments of signal net interconnect, enhancing the quality of results available to designers.

MOS Reliability Option (MOSRA)
Fragile nanometer transistors are stressed by high field strengths in the device channel, by high temperature, and by high-frequency switching activity over extended periods of time. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) are two effects that can lead to device parameter variation over time, resulting in performance degradation and designs failing to meet specification. The MOSRA option offers flexible support for these stress effects by providing both standard and user-specified aging equations as extensions to industry-standard BSIM3 and BSIM4 models. Using MOSRA enables users to measure performance degradation over time, by comparing the results of pre-stress and post-stress simulation results.

HDL Co-Simulation Option
HSIM^plus supports integration with popular RTL and gate-level simulators, such as NC-Sim from Cadence Design Systems or ModelSim from Mentor Graphics, for enhanced mixed-level full-chip verification containing a mixture of RTL, gate-level and transistor-level circuit descriptions. Using the industry standard Verilog Programming Interface, the integration supports both top-down and bottom-up verification flows by allowing for either the digital or circuit-level representation to be the top-level view for the design. Verilog or VHDL test-benches can also be run directly with HSIM, and do not require a separate digital simulation and translation step by verification engineers. Click here to learn more about Co-Simulation.

CircuitCheck Option
CircuitCheck screens, identifies and reports any potential circuit design problems, both before and during circuit simulation. Such checks include excessive rise and fall delays; DC leakage paths; un-initialized latches; potential crosstalk noise problems; and user-specified dynamic checks for incorrect conditions of circuit operation, such as over-voltage conditions. CircuitCheck enhances user productivity by assisting in the debugging of simulation failures reported by HSIM, including finding sources that trigger changes in circuit outputs. CircuitCheck can save design teams days and weeks of debug time.

The HSIM^plus Solution
HSIM^plus is a comprehensive transistor-level simulation and analysis platform for pre-layout design and post-layout verification of nanometer integrated circuits. HSIM^plus expands on the mature, robust and production-proven HSIM simulator to address the most critical problems associated with the physical effects of interconnect wiring and short-channel devices. The architecture of HSIM^plus has been developed to satisfy the rigorous requirements of the most demanding users. Not just today, as these users enter the nanometer age, but also in the future at 65nm and below.

Through its hierarchical analysis, the HSIM simulator provides the capacity and throughput needed for large and complex nanometer circuits. HSIM uses the same device models as reference simulators such as SPICE and Spectre with this innovative hierarchical technology. As a result, accuracy is not sacrificed for the sake of performance or capacity. Designers now have the simulator they need for their demanding analog, mixed-signal, memory and SoC designs. HSIM is ideal for simulating, at the circuit level, designs with tens to hundreds of millions of transistors, including video and network processors; DSPs; mixed-signal SoCs; and discrete and embedded memories such as Flash, SRAM, DRAM, and CAM. Another strength of HSIM is in analyzing A/D and D/A converters, switched-capacitor filters, phase-locked loops, charge pumps, high-speed transceivers and designs of several thousand transistors which have extremely long simulation times when using SPICE tools. For these sensitive circuits, HSIM typically reduces run-times from days to hours, even minutes. HSIM can accurately simulate circuit functionality, voltage and current waveforms, and timing and power behavior. Not just a transient simulator, HSIM includes IDDQ power leakage, smallsignal AC, and Monte Carlo statistical analyses. The HSIM^plus platform offers a complete design analysis tool for analog and mixed-signal design.

Ease Of Adoption
HSIM^plus integrates easily into customers?existing design environments. Circuit data from these design flows, including netlists and extracted data in DSPF or SPEF formats, is read directly into HSIM^plus without editing or other manipulation. HSIM uses industry standard MOS device models and used in the same way as a SPICE tool.

Behavioral Modeling
Verilog-A behavioral modeling of design blocks is also natively supported in HSIM, and a built-in compiler speeds simulation and analysis. Simulation of models described in the Verilog-A language permits rapid development and verification of analog behavioral models for new device types or circuit blocks. Additionally, for functional modeling at even higher levels of abstraction, HSIM incorporates a compiled C-language interface that allows an entire circuit block, such as a D/A or A/D converter, to be coded as single C-routine for greater simulation efficiency.

Post-Layout Verification and Analysis
Today抯 fine-line nanometer processes employ complex multi-layer metallization structures and advanced dielectric materials. The impact of new materials, and closely-spaced, tall, thin metal interconnect combined with design characteristics such as high edge rates and low power supply voltage, means that first silicon success depends on detailed verification including the parasitic components extracted from layout.

The physical effects of wire delay in nanometer interconnect began to dominate over gate delay at the 180nm process node. Today, with many designs moving to 130nm and below, these effects become even more significant as the coupling effects of parasitic capacitance between neighboring wires degrade signal integrity and introduce delay that is dependent on activity in adjacent signal nets. In addition, device scaling requires power supply voltages to be further reduced, and parasitic power net resistance causes IR drop, degrading supply headroom and increasing signal drive requirements. This dynamic voltage drop causes design characteristics, such as memory access time or the critical path delay in logic, to degrade during 憂ormal?circuit operation. In the worst case, successfully verified designs will be manufactured at performance levels way below those specified (and verified using alternative methodologies), and possibly result in zero yield. Additionally, once deployed into end products and systems, high current density causes electro-migration in narrow interconnect structures, resulting in fatal design failure and a lifetime that can be measured in months rather than decades. In order to accurately analyze each of these effects, full-chip post-layout simulation with extracted parasitic components is necessary.

Figure 3. HSIM post layout flow

HSIM^plus offers a wide range of post-layout simulation options, and provides the capacity and efficiency to handle the huge amount of data that is in the extracted parasitic files for nanometer ICs. HSIM抯 unique RC reduction methods can deal with even the largest and most complex power nets containing hundreds of millions of resistors, and signal nets containing tens of millions of coupling capacitors in addition to resistors and grounded capacitors, while maintaining the benefits of hierarchical simulation performance, precision and memory efficiency.

Summary
The value of producing first nanometer silicon success, tape-out after tape-out, cannot be underestimated. Without comprehensive, high-integrity verification and analysis that include the detailed impact of full-chip layout parasitic elements, the rate of first silicon success for nanometer designs continues to fall. The cost to identify and resolve a dynamic nanometer effect can run from hundreds of thousands to millions of dollars. The opportunity cost, in missed market window and lost revenue, can be many millions of dollars. Incorporating HSIM^plus as a crucial part of your verification flow reduces the risk of failure, and significantly increases the chances of nanometer silicon success.

Platform Support
HSIM^plus is offered on workstations running Solaris, HP-UX, Windows NT/2000/XP, and Linux operating systems.