DLI PUSHES AHEAD PLDS AND FPGAS DEBUG AND VERIFICATION CAPABILITIES!
By introducing On Chip Instrumentation (OCI) tools on the market for any type of FPGAs, Temento Systems brings to the designer a new way to monitor and to debug complex designs. In the DLI environment, you can seamlessly choose your instrumentation inside the DLI Core Library and embed it into your design.
After downloading your design file and the instrumentation into your FPGA, DLICore Control and Display Tools allows you to debug, analyze logic signals and transactions, monitor busses and record logic events. DiaLite is now includes all features of the Leading Edge Edition plus the HDL Fault Finder module. The HDL Fault Finder allows the designer to insert Watchpoints and Breakpoints into the HDL code and run concurrently to the instrumentation. The HDL Fault Finder provides an accurate monitoring and display of logic events occuring during the debug process. The insertion of watchpoints in your HDL code allows you to trace all events and quickly focus on the faulty lines of code.
REAL TIME & FASTER ON-CHIP DEBUGGING
With its powerful and wide range of IP cores, DLI increases the verification and debugging capabilities of your FPGAs designs or System on Programmable Chip (SoPC) designs.DLI actually embeds triggers, bus traffic analyzers, glitch detectors, multi conditional triggers,etc... in your design and according to your debug strategy. These cores allow you to view all the internal signals and nodes within the FPGA. Users can combine multiple assemblies of IP cores, multiple triggers conditions to build their own specific instrumentation and capture data at the system clock rate. With an easy connection to your usual tools like BDM and debuggers, a DLI based strategy can save months of your co-debug effort !
GET ALL BENEFITS FROM DIALITE EDITIONS
Using one of the DLI Rev 4.5 Editions, you will be able to set up a full internal observability on the behavior of your design.
DLICore Generator : allows easy choice and free assembly of the IP instruments cores to build complex measuring chains. DLI Core Insertor : gives the user the possibility to insert instruments IP cores in VHDL or Verilog languages and guarantees automatic connection to the signal nodes. DLICore Control and Display : provides monitoring and direct display of the data issued from the embedded IP cores.
Using the capability to view and display multiple instruments simultaneously on multiple FPGA, you will get a powerful software debugging environment not available from any other provider.
DLI GUARANTEES A TOTAL INDEPENDENCE FROM FPGA MANUFACTURER, EDA TOOLS PROVIDER AND PLD TECHNOLOGY
Using HDL IP cores directly in your design, DLI guarantees your independance whatever the type of FPGA you are using on your board. Compatible with any synthesis tools and software suite, you get total flexibility to use DLI with Actel, Altera, Lattice, Xilinx or other FPGA manufacturers implemented on your board.
HIGHLIGHTS
- Multi-vendor independent platform
- Distributed instrumentation on multiple device
- User-definable flow of IP core instruments
- Supports any Xilinx, Altera, Lattice, Actel and other FPGA devices or a mixed of them
- Real synchronization with other tools like BDM and C Debugger
- Multi-languages VHDL (1076.1) and Verilog (1364) design descriptions or a mixed of both
- Debug design at the full system clock speed.
- Dynamically change trigger and data probes during debug
- Supports DCOM scripting interface (C, TCL, Perl)
- Easy tool start-up sequence
- User Friendly Interface
- Large choice of instruments
- Fully compliant with Xilinx ISE, Altera Quartus II, Actel Libero, Lattice ISP Lever and other design flows
- Fully compatible with major market synthesis tools (Synopsis, Mentor Graphics, Synplicity and others)
- Parallel port cable, USB module or PCI hardware controller interface
- Delivered with Windows NT/2K/XP drivers.
WHAT'S NEW IN REV 4.5?
- Full independence of System (GCLK) & JTAG (TCK) clocks
- Step by step Debug Mode : instruments results can be read even when GCLK is stopped
- Declaration of passive components within JTAG chain
- Support of Xilinx Native TAP (Spartan : 3, II, IIE; VIRTEX : E, II, II Pro)
- New Wizard to facilitate the project creation
- The support of project Import/Export for Synplify Pro, Libero, ISE in addition to Quartus II and Design Compiler FPGA
- Signal Find Option
- Enhanced display & positioning of HDL Fault Finder Breakpoints & Watchpoints