The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16750S can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.
Developed for easy reuse in ASIC and FPGA applications, the H16750S is available optimized for several device families with competitive utilization and performance characteristics.
Features
Capable of running all existing 16450 and 16550a software
Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU
Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
Independently controlled transmit, receive, line status and data set interrupts
Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock
Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn)
Programmable Auto-CTSn and Auto-RTSn
In Auto-CTSn mode, CTSn controls the transmitter
In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
Fully programmable serial interface characteristics:
5, 6, 7, or 8 bit characters
Even, odd, or no-parity bit generation and detection
1, 1.5, or 2 stop bit generation
Baud generation
False start-bit detection
Complete status register
Internal diagnostic capabilities: loop-back controls for communications link fault isolation
Full prioritized interrupt system controls
Applications
The H16750S can be utilized for a variety of applications including:
Serial or modem computer interface
Serial interface within modems and other devices
Symbol Diagram
Block Diagram
Functional Description
As shown in the block diagram and explained below, the H16750S includes seven major blocks: Interface, Registers, RXBlock, Interrupt Control, Baud Rate Generator, TXBlock and IrDA. All inputs and outputs for the H16750S are fully synchronous to the rising edge of the CLK input.
Interface
The Interface block is responsible for handling the communications with the processor (or parallel) side of the system. All writing and reading of internal registers is accomplished through this block.
Registers
The Registers block holds all of the device’s internal registers. See the Register Description table for details on existing registers and their addresses. Some information comes from the other blocks, however register information is gathered in the Registers block and made available to all blocks.
RXBlock
This is the receiver block. RXBlock receives the incoming serial word. It is programmable to recognize data widths such as 5, 6, 7 or 8 bits, various parity settings such as even, odd or no parity, and different stop bits such as 1, 1.5 and 2 bits. RXBlock checks for errors in the input data stream such as overrun errors, frame errors, and parity errors and break errors. If the incoming word has no problems, it is placed either in the Receiver Holding register or in the Receiver FIFO depending on the mode programmed.
Interrupt Control
The Interrupt Control block sends an interrupt signal back to the processor depending on the state of the FIFO and its received and transmitted data. The Interrupt Identification register provides the level of the interrupt. Interrupts are sent in the condition of empty transmission/receiving buffers (or FIFOs), an error in receiving a character, or other conditions requiring the attention of the processor.
Baud Rate Generator
This block takes the input clock (CLK) and divides it by a programmed value (from 1 to 216 – 1). The result is then divided by 16 to create the transmission clock (Baudout clock).
TXBlock
The Transmit block handles the transmission of data written to the Transmission Holding register (or transmit FIFO). It adds required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper error handling and receiving.
IrDA
The IrDA block is an optional addition to the H16750. It handles the same data as the SIN and SOUT only in an Infra Red Interface format.
Implementation Results
H16750S reference designs have been evaluated in a variety of technologies. The following are sample ASIC results:
ASIC Technology
Approx.
Area
Frequency
(MHz)
TSMC 0.18μ
18857 gates
250
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Wrapper for pin compatible replacement
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide
