CZ80PIO Programmable Parallel I/O
Controller Core
Description | Features | Applications | Symbol | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The CZ80PIO, hereinafter referred to as PIO, is a dual-port device which can be programmed by the system software to function as a broad range of peripheral devices that are compatible with the Z80CPU such as most keyboards, printers etc.
System design is simplified because the PIO connects directly to the Z80CPU with no additional logic. In larger systems, address decoders and buffers may be required.
The CZ80PIO is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous, with no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
Features
- Provides a direct interface between Z80 microprocessor systems and peripheral devices
- Two ports with interrupt-driven handshake for fast response
- Four programmable operating modes:
- Output Mode (both ports)
- Input Mode (both ports)
- Bi-directional (Port A only)
- Bit Control Mode (both ports)
- Programmable interrupts on peripheral status conditions
Applications
The CZ80CPU core can be utilized for many embedded controller applications including:
- Programmable, dual - port device
- Interface for a wide range of peripheral devices such as keyboards, printers, paper table readers, PROM programmers etc.
Symbol Diagram
Block Diagram
Functional Description
The CZ80PIO core is partitioned into modules as shown in the block diagram and described below.
Port Logic
Each port contains separate input and output registers, handshake control logic and the control registers. All data transfers between the peripheral unit and the CPU use the data input and output registers. The handshake logic associated with each port controls the data transfers through the input and the output registers. The mode control register (two bits) selects one of the four programmable operating modes. The Bit Control mode (mode 3) uses the remaining registers. The input/output control register specifies which of the eight data bits in the port are to be outputs and enables these bits; the remaining bits are inputs. The mask register specifies which of the bits in the port are masked.
Control logic
The control logic consists of the CPU bus interface logic, interrupt control logic and internal control logic. The CPU bus interface logic interfaces the CZ80PIO directly to the CZ80CPU, so no external logic is necessary. For large systems, however, address decoders and/or buffers may be necessary. The interrupt control logic section handles all CPU interrupt protocol for nested-priority interrupt structures. Any device's physical location in a daisy-chain configuration determines its priority. Two lines (IEO and IEI) are provided in each PIO to form this daisy chain. The device closest to the CPU has the highest priority. Within a PIO, port A interrupts have higher priority then those of port B. In the byte input, byte output or bi-directional modes, an interrupt can be generated whenever the peripheral requests a new byte transfer. In the bit control mode, an interrupt can be generated when the peripheral status matches a programmed value.
Implementation Results
CZ80PIO reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The CZ80PIO core’s functionality was verified by means of a proprietary hardware modeller. The same stimulus was applied to a hardware model that contained the original Zilog Z80PIO chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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