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CZ80CTC Programmable Counter/Timer

Core

Description | Features | Applications | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables

The CZ80CTC Programmable Counter Timer (CZ80CTC) is a four-channel counter/timer that can be programmed by system software to perform a broad range of counting and timing applications. The four independently programmable channels of the CZ80CTC satisfy common microcomputer system requirements for event counting, interrupt and interval timing, and clock rate generation.

System design is simplified because the CZ80CTC connects directly to the CZ80SIO with no additional logic. Larger systems may require address decoders and buffers.

Features

• Control Unit: 8-bit Instruction decoder
• Four independently programma-ble counter/timer channels, each with:
  • readable downcounters
  • selectable 16 or 256 prescaler
  • downcounters are reloaded automatically at zero count
• Selectable positive or negative trigger initiates timer operation
• Interfaces directly to the CPU or for baud rate generation to the Z80 SIO
• Standard Z80 Family daisy-chain interrupt structure pro-vides fully vectored prioritized interrupts without external logic. The CTC may used as an interrupt controller
• Synchronous design without internal tri-states and a synchronous reset

Applications

The CZ80CTC can be utilized for a variety of applications including:

• Programmable frequency divider
• Pulse counter
• Programmable pulse generator
• Interrupt controller
• Programmable events generator

Block Diagram

Functional Description

The CZ80CTC core is partitioned into modules as shown in the block diagram and described below.

Bus Control Unit

The bus control unit decodes the channel address inputs, and interfaces the CPU data and control signals to the write control, time-constant and vector words to the internal registers.

Counter_Timer Unit

The four Counter_Timer shown in the block diagram are part of this unit. Each Counter_Timer consists of:

• Prescaler - The precsaler, is used only in the timer mode. It divides the system clock frequency by a factor of either 16 or 256. The prescaler output clocks are decremented by the downcounter during the timer operation.
• Downcounter – The downcounter is loaded with the time-constant register contents and then decrements its own value by one in two ways, depending on the operating mode: from prescaler – in timer mode; from clktrg inputs – in counter mode. At zero count, the time constant value is automatically loaded into the downcounter. When the downcounter reaches zero, the zcto output generates a positive going pulse. When the interrupt is enabled, zero count also triggers an interrupt request signal int from the Interrupt Control.

Interrupt Control

This unit controls the interrupt priority of the CTC as a function of the iei signal. If iei is high, the CTC has priority. During interrupt processing, the interrupt holds ieo Low, to inhibit the interrupt operation for the lower priority devices.

Ent_fall

This unit is used to form the correct timing of int and zcto sig-nals (they change on both edges). In all designs, only four registers work on the falling edge of clock, and they are placed in this unit.

Implementation Results

CZ80CTC reference designs have been evaluated in a variety of technologies.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The CZ80CTC core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Zilog Z84C30 chip and the results compared with the core’s simulation outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide