C8259AS Synchronous Programmable
Interrupt Controller Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The C8259AS Synchronous Programmable Interrupt Controller core implementation manages up to 8-vectored priority interrupts for a Processor. Using multiple instantia-tions of the core and programming it to cascade mode allows for up to sixty-four vectored interrupts. More than sixty-four vectored interrupts can be accomplished by programming the core to Poll Command Mode.
Features
- Eight vectored priority interrupts per core. Up to sixty-four vectored priority interrupts with cascading.
- Programming for all 8259A modes and operational features:
- MCS-80/85 and 8088/8086 processor modes
- Fully nested mode and special fully nested mode
- Special mask, Buffered and Pool command modes
- Cascade mode with master or slave selection
- Automatic end-of-interrupt mode
- Specific and non-specific end-of-interrupt commands
- Automatic & Specific Rotation
- Edge and level triggered interrupt input modes
- Reading of interrupt request register (IRR) and in-service register (ISR) through data bus
- Writing and reading of interrupt mask register (IMR) through data bus
- CLKOUT input for easier integration with 386EX
- The C8259AS is available in VHDL or Verilog and synthesizes to approximately 2,400 gates depending on the process used.
- Functionally based on the Intel 8259A and Harris 82C59A devices
Applications
The C8259AS core is used in real time interrupt driven microcomputer designs.
Symbol Diagram
Block Diagram
Functional Description
The C8259AS core is partitioned into modules as shown above in the block diagram and described below:
Data Bus Buffer
This 3-state, bi-directional 8-bit buffer is used to interface the C8259AS core to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer.
Read / Writer Logic
The function of this block is to accept output commands from the CPU. It contains the initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the C8259AS core to be transferred onto the Data Bus.
Cascade Buffer Comparator
This block stores and compares the Ids of all C8259AS’s used in the system. The associated three I/O pins (CAS0-2) are outputs when the C8259AS is used as a master and are inputs when the C8259AS is used as a slave. As a master, the C8259AS core sends the ID of the interrupting slave de-vice onto the CAS0-2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data during the next one or two consecutive INTAn pulses.
Control Logic
This block checks for INTAn pulses, which cause the C8259AS to release vectoring information onto the data bus. The format of this data depends on the system mode of the C8259AS. This block also sets the interrupt output high whenever a valid interrupt request is asserted.
Interrupt Request Register (IRR) & In-Service Register (ISR)
The interrupts at the IR inputs lines are handled by two regis-ters in cascade, the Interrupt Request Register (IRR) and the In-Service Register (ISR). The IRR is used to store all the in-terrupt levels which are requesting service. The ISR is used to store all the interrupt levels that are being serviced.
Priority Resolver
This block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corre-sponding bit of the ISR during an INTAn pulse.
Interrupt Masking Register (IMR)
The IMR stores the bits that mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality.
CLKOUT Signal
The input pin CLKOUT is available to facilitate connectivity to 386EX devices. In such systems this pin should be con-nected directly to the 386EX CLKOUT pin. In other systems this pin should be tied to VCC. Note that the CLKOU input pin acts as an enable to the device. It should not be speci-fied as a CLK pin in your synthesis tool.
Synchronization
IR inputs are asynchronously accepted by the C8259AS core, but synchronized to the rising edge of CLK through two flip-flops before further processing within the core. This is to help protect against metastability.
Input signals RDn, WRn, CSn, A0, D(7:0), INTAn and output signal INT are synchronous to CLK. The input signals, when active, are accepted on the rising edge of CLK AND CLKOUT = 0. Signal CLK is the clock to the flip-flops while CLKOUT is a register enable.
Implementation Results
C8259AS reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C8259AS Interrupt Controller core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that con-tained the original Intel 8259A chip, and the results compared with the core’s simulation outputs (accounting for the syn-chronous implementation of this device).
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
|
