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C8259A Programmable Interrupt

Controller Core

Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables

The C8259A Programmable Interrupt Controller core manages up to 8 vectored priority interrupts for a Processor. Using multiple instantiations of the core and programming it to cascade mode allows for up to sixty-four vectored interrupts. More than sixty-four vectored interrupts can be accomplished by programming the core to Poll Command Mode.

Features

• Eight-vectored priority interrupts per core. Up to sixty-four vectored priority interrupts with cascading
• Programming for all 8259A modes and operational features:
  • MCS-80/85 and 8088/8086 processor modes
  • Fully nested mode and special fully nested mode
  • Special mask mode
  • Buffered mode
  • Pool command mode
  • Cascade mode with master or slave selection
  • Automatic end-of-interrupt mode
  • Specific and non-specific end-of-interrupt commands
  • Automatic & Specific Rotation
  • Edge and level triggered interrupt input modes
  • Reading of interrupt request register (IRR) and in-service register (ISR) through data bus
  • Writing and reading of interrupt mask register (IMR) through data bus
• The C8259A is available in VHDL and Verilog and synthesizes to approximately 2,400 gates
• Functionally based on the Intel 8259A and Harris 82C59A devices

Applications

The C8259A can be utilized in a variety of interupt controller applications.

Symbol Diagram

Block Diagram

Functional Description

The C8259A core is partitioned into modules as shown in the block diagram and described below:

Data Bus Buffer

8-bit input and output buffer is used to interface the C8259A core to the system Data Bus. DEnb controls data bus direction. Control words and status information are transferred through the Data Bus Buffer.

Read / Write Logic

The function of this block is to accept output commands from the CPU. It contains the initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the C8259A core to be transferred onto the Data Bus.

Cascade Buffer Comparator

This block stores and compares the Ids of all C8259A’s used in the system. The CASEnb will control CAS[2:0]. CAS[2:0] are outputs when the C8259A is used as a master and are inputs when the C8259A is used as a slave. As a master, the C8259A core sends the ID of the interrupting slave device onto the CAS0-2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data during the next one or two consecutive INTAn pulses.

Control Logic

This block checks for INTAn pulses, which cause the C8259A to release vectoring information onto the data bus. The format of this data depends on the system mode of the C8259A. This block also sets the interrupt output high whenever a valid interrupt request is asserted.

Interrupt Request Register (IRR) & In-Service Register (ISR)

Two registers in cascade, the Interrupt Request Register (IRR) and the In-Service Register (ISR), handle the interrupts at the IR inputs lines. The IRR is used to store all the interrupt levels, which are requesting service. The ISR is used to store all the interrupt levels that are being serviced.

Priority Resolver

This block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during an INTAn pulse.

Interrupt Masking Register (IMR)

The IMR stores the bits that mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality.

Implementation Results

C8259A reference designs have been evaluated in a variety of technologies.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C8259A Interrupt Controller core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 8259A chip, and the results compared with the core’s simulation outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide