C8255A Programmable Peripheral
Interface Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The C8255A programmable peripheral interface core implements a general-purpose I/O interface to connect peripheral equipment to a microcomputer system bus. The core’s functional configuration is programmed by the system software so that external logic is not required to interface peripheral devices.
Features
- Three 8-bit Peripheral Ports - Ports A, B, and C
- Three programming modes for Peripheral Ports: Mode 0 (Basic Input/Output), Mode 1 (Strobed Input/Output), and Mode 2 (Bidirectional)
- All ports are set to input after a reset
- Total of 24 programmable I/O lines
- 8-bit bidirectional system data bus with standard microprocessor interface controls
- Developed in VHDL and synthesizes to approximately 1,000 gates depending on the on the process used
- Functionally based on the Intel 8255A device
Applications
The C8255A can be utilized to facilitate Processor I/O.
Symbol Diagram
Block Diagram
Functional Description
The C8255A core is partitioned into modules as shown in the block diagram and described below:
Data Bus Buffer
This 3-state bi-directional 8-bit buffer is used to interface the core to the system data bus. Data is transmitted or re-ceived by the buffer upon execution of input or output instructions by the CPU. Control words and status informa-tion are also transferred through the data bus buffer.
Processor Read/Write Control
The function of this block is to manage all of the internal and external transfers or both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and it turn, issues commands to both of the Control Groups.
Control Word Register
The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a con-trol word to the core. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the core.
Ports
The C8255A core contains three 8-bit ports. All can be con-figured in a wide variety of functional characteristics by the system software but each has its own special features.
- Port A: One 8-bit data output latch/buffer and one 8-bit input latch buffer.
- Port B: One 8-bit data input/output latch/buffer.
- Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be di-vided into two 4-bit port under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B.
Implementation Results
C8255A reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C8255A core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was ap-plied to a hardware model which contained the original Intel 8255A chip, and the results compared with the core’s simu-lation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Wrapper for pin compatible replacement
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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