C2910A Microprogram Controller Core
Description | Features | Applications | Symbol | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The C2910A microprogram controller core is an address sequencer that controls the sequence of execution for the microinstructions stored in microprogram memory. The core can sequentially access the microinstructions, and it provides conditional branching to any microinstructions within the 4,096-microword range. In addition, a nine-deep LIFO stack provides a microsubroutine return linkage and looping capability.
Features
- 12-bit data width that addresses up to 4,096 words
- Internal Loop Counter - Pre-settable 12-bit down-counter for repeating instructions and counting loop interactions
- Four Address Sources - Microprogram Address may be selected from microprogram counter, branch address bus, 9-level push/pop stack, or internal holding register
- 16 powerful microinstructions
- Output Enable Controls for Three Branch Address Sources
- Positive-edge-triggered registers
- Available in VHDL or Verilog
- Functionality based on the Advanced Micro Devices AM2910A
Applications
The C2910A core is used in high-speed bit-slice designs.
Symbol Diagram
Block Diagram
Functional Description
The C2910A core is partitioned into modules as shown in the block diagram and described below.
Multiplexer
The four-input multiplexer is used to select either the register/counter, direct input, microprogram counter, or stack as the source of the next microinstruction address.
Register Counter
This block consists of 12 D-type, edge-triggered flip-flops, with a common enable. When its load control, RLDN is low, new data is loaded on a positive clock transition. The output of the register/counter is available to the multiplexer as a source for the next microinstruction address. The direct input furnishes a source of data for loading the register/counter.
Microcontroller Counter/Register (μPC)
This block consists of a 12-bit incrementer followed by a 12-bit register. The μPC can be used in either of two ways: When the carry-in to the incrementer is high, the microprogram register is loaded on the next clock cycle with the current Y output word plus one (Y + 1 -> μPC). Sequential microinstructions are thus executed. When the carry-in is low, the incrementer passes the Y output word unmodified so that μPC is reloaded with the same Y word on the next clock cycle (Y -> μPC). The same microinstruction is thus executed any number of times.
Stack
This 9-word by 12-bit stack is used to provide return address linkage when executing microsubroutines or loops. The stack contains a built-in stack pointer which always points to the last word written. This allows stack reference operations (looping) to be performed without a pop.
Instruction Decoder
This block decodes the incoming instruction and generates the appropriate control signals for all the other blocks. The instruction decoder block also generates the outputs PLN, MAPN, and VECTN.
Implementation Results
C2910A reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C2910A core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model which contained the original AMD 2910A chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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