LJPEG-E Lossless JPEG Encoder Core
Description | Features | Applications | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The LJPEG-E core implements Lossless JPEG (LJPEG) compression in a compact, high-performance, stand-alone package ideal for applications where bit-by-bit accurate reproduction of an image is essential.
The LJPEG-E conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression—which can introduce round-off errors—the LJPEG-E employs a predictor function as described in the specification. It thus encodes and compresses images with no information loss, and requires a significantly smaller physical implementation.
Evaluation designs show that the core requires only 32K gates in an ASIC (typical 0.18μ process) and that it fits in a variety of low-cost FPGA devices. Its heavily optimized architecture also enables very high performance, reaching 300 MSamples/sec.
The LJPEG-E is a fully synchronous, strictly positive-edge design with no internal three-state buffers. Comprehensive documentation and a complete verification environment—including a bit-accurate model—help designers integrate and verify the core.
Features
- Conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation).
- Standalone operation.
- Pixel input.
- ISO/IEC 10918-1 JPEG stream output.
- Easily programmable through standard JPEG markers stream.
- Programmable image dimensions.
- Up to four stream-programmable Huffman tables.
- Programmable restart interval.
- Programmable point transform function.
- Programmable APPn and COM markers.
- Header error catch-up features.
- Compact, high-performance architecture.
- 32K gates achieving 300 MSamples/sec (0.18μ ASIC)
- Also fits inexpensive FPGAs (see FPGA version datasheets)
- Robust and simple to use
- General purpose, fully stallable I/O interfaces.
Limitations with respect to the ISO/IEC 10918-1 standard:
- Up to three image-components are supported (Nf field of the SOF3 marker segment = 1 or 2 or 3).
- Single scan encoding (only one SOS marker segment, with Ns field = Nf).
- No DNL marker insertion (Y field of the SOF3 marker segment > 0).
- Fixed parameters.
- Supported sample precision is fixed to 16 bits (P field of the SOF3 marker segment = 16).
- No sub-sampling (Hi and Vi fields of the SOF3 marker segment = 1).
- Prediction function is fixed to the left-hand predictor, predictor 1. (Ss field of SOS marker segment = 1).
Applications
The LJPEG-E provides a fast, economical solution whenever lossless image compression is essential, including applications such as:
- Medical, military, and space imaging.
- Professional, studio-quality cameras and editing suites.
- High-end film and photo scanners.
- Industrial machine vision systems.
Block Diagram
Functional Description
Lossless JPEG was added to the ITU-T JPEG recommendations in 1995. The JPEG lossless mode of operation does not use the 2D-DCT that is used in the lossy mode, since round-off errors prevent a 2D-DCT calculation from being lossless. For the same reason, one would not normally use color space conversion or downsampling, although these are permitted by the standard.
The lossless mode of the standard codes the difference between each pixel and the "predicted" value for the pixel. The predicted value is a function of the already-transmitted pixels just above and to the left of the current one (eight different predictor functions are defined in the standard). The sequence of the calculated differences (prediction errors) is encoded using the same back end (Huffman or arithmetic) used in the lossy mode.
The LJPEG-E implements the predictor 1 function of the standard, and the Huffman coding back end.
The LJPEG-E is initially configured using standard JPEG marker segments from the configuration stream input interface. It is configured for frame properties using a standard SOF3 marker segment. Huffman tables that will be used for encoding are programmed through one or more DHT segments. If the restart interval and/or point transform functions are required, they are programmed through the standard DRI and SOS marker segments respectively. If the application needs to use comment and/or application markers, then these are programmed using COM and/or APPn segments and the LJPEG-E will include them in the output stream.
After initial configuration, the LJPEG-E is ready to accept and encode image frames. Pixel data are written to the core through the pixel input interface and the compressed data are output through the JPEG stream output interface. Configuration can remain constant between consecutive frames or it can change to meet specific frame requirements. In the compressed output stream, the LJPEG-E includes all the necessary markers so the produced stream is a full, stand-alone JPEG stream that can be decoded by any ISO/IEC 10918-1 compliant lossless JPEG decoder.
Implementation Results
The LJPEG-E core has been evaluated in a variety of technologies and devices. Synthesis results targeting indicative 0.18u ASIC processes and using balanced area/speed constraints show that the LJPEG-E requires just 32K gates (excluding internal memories) and runs at 300MHz, processing 300 MSamples/second.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation using a large set of test vectors and reference results, and through rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- A bit-accurate model (BAM) including custom vector generation support, and a software library of the bit accurate model functions
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- An RTL simulation model
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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