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LB_2DFDWT Line Based Forward

Discrete Wavelet Transform Core

Description | Features | Applications | Block Diagram | Functional Description | Core Modifications | Implementation Results | Support | Verification | Deliverables

The LB_2DFDWT core operates by internally buffering the minimum number of the input image lines required to perform the transformation. This makes it ideal for applications where the image is not available as a complete frame in memory, such as when scanning a picture, or receiving a picture. Using the LB_2DFDWT core in such applications, allows the image to be processed progressively as it is loaded, so that the transformed image is available as soon as the input image has been delivered.

The results of the transformation are internally buffered to a FIFO and are sent to the output sequentially. The rate of the output is user-configurable and it is set to about the mean rate at which the results are produced. This permits the interfacing with single port memories, slower than the system clock of the LB_2DFDWT core. Sub-band and level information is provided too, for custom manipulation of the results.

The LB_2DFDWT core delivers a fast implementation of the line based DWT algorithm, without sacrificing internal FPGA memory space. The main objective while designing the core architecture was to achieve effective internal memory utilization, so that the largest possible image can be processed for a given amount of RAM in the FPGA. As a result, the core can fit in smaller and cheaper FPGAs. Note that the Line Based Algorithm has more needs for on-chip memory than logic and the size of the FPGA that must be used is mostly specified by the amount of the internal RAM Blocks available.

The LB_2DFDWT core is accompanied by fully parameterized and documented VHDL source code, which supports all possible options. The image dimensions and the levels of transformation are user programmable up to a maximum limit that is defined via VHDL generics values.

Features

• Streaming of the input. Wavelet trans-formation begins after a minimum number of image lines are available
• Streaming of the output
  • The results are internally buffered and sent to the output sequentially
  • Addressing to store the results in an external SRAM is internally generated
• Very fast implementation with the lowest possible utilization of internal FPGA memory
• Provided with easy to use, fully parameterized VHDL source code, supporting:
  • 9/7 or 5/3 filters
  • User defined image dimensions, which can be a multiple of 2MAX_LEVELS
  • User defined bitwidths for the filtering unit data path and the input pixels
  • Levels of transformation
• Wait states for writing the results to an external memory

Applications

The LB_2DFDWT core implements the Forward 2-Dimensional Discrete Wavelet Transform, using the convolutional 9/7 filters. The LB_2DFDWT core is based on the Line Based computational architecture. The main advantage with this architecture is that it’s not necessary to have the whole image stored in a frame buffer to begin the transformation. The image is transformed progressively from top to bottom while it is loaded, so that the transformed image results are available as soon as the input image has been delivered. This makes it ideal for applications where the image is not available as a complete frame in memory, such as when scanning or receiving a picture sequentially from top to bottom. The LB_2DFDWT core supports the standard JPEG2000 tile parameters.

Block Diagram

Functional Description

The core is initialized and programmed with the user desired image size and levels of decomposition. Then the core begins the transformation procedure, after a pulse is sent to the Start_frame input. External hardware is signaled whether it is allowed to write input image pixels to the core. The external hardware transfers the input image to the core sequentially, line by line from top to bottom. After a certain number of lines have been written to the core, they can be processed. While the core is processing, the external hardware is not allowed to send any image pixels. When the processing of the image lines that are stored in the core’s line buffers has finished, the core signals the external hardware to proceed on sending additional image pixels. Meanwhile, the core outputs the transformation results to an external RAM that is used to store the transformed image frame. When the core has finished processing the frame, a pulse is generated to notify that it can proceed with a new frame.
The core acts as a slave when reading image data, and can be operated either as a master or a slave when writing the results to the external RAM.

The block diagram of the LB_2DFDWT core is shown above.

Pixel Line Buffer (PLB), Coefficient Line Buffer (CLB)

The core includes two large memory buffers. PLB is used to buffer the input image lines and CLB is used to store the intermediate results of the Wavelet Transform. The buffers incorporate a mechanism, which fetches automatically the data to be filtered by the Filtering Units. The data involved in vertical filtering can be fetched while the horizontal filtering of the previous data takes place.

Filtering Unit

The filtering unit, implements the Daubechies 9/7 convolutional filters. The filter coefficients are quantized after extensive experimental exploration to achieve accurate results without wasting hardware.

Mirroring Module

A Mirroring Module is used ahead of the Filtering Unit to permute the filter input data, during the initialization and finalization phases of the Wavelet Transform scan.

Horizontal Filtering FIFOs

The two Horizontal Filtering FIFOs consist of registers and are used to buffer the results of the vertical Wavelet Transformation scan for the horizontal scan.

Output FIFO

The output results are internally produced in pairs. To avoid using a dual port memory to store the output results, the results must be sent to the output sequentially. To achieve this, the transformation results are internally buffered into a dual input, single output FIFO.

Addressing Module

A module that generates the addressing in order to write the results into an external RAM is provided to facilitate the manipulation of the results.

Control Unit

The control unit activates the internal modules and supplies them with the correct input, according to the line-based algorithm. The input / output bus interface is also implemented in the control unit. The parameters of the transformation such as the image size and the levels of the transformation are programmed via the input/output interface.

Core Modifications

The LB_2DFDWT core can be easily customized from the supplier to meet application specific requirements, such as other than the specified maximum image dimensions or maximum levels.

At additional cost, other modifications are possible such as custom filter coefficients or a 5/3 filtering unit, which is already available. Also, fully parameterized VHDL RTL source code is available.

Please contact CAST directly for any required modifications.

Implementation Results

LB_2DFDWT reference designs have been evaluated in a variety of technologies

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The LB_2DFDWT core’s functionality was verified by means of a VHDL testbench and a set of software utilities to compare the results with the theoretical. The verification flow is the following.

• Run forward DWT in software with a very accurate filter implementation. The results are stored for comparison with the results of the core’s simulation.
• The VHDL testbench is compiled and simulated, using the same input image as the software DWT.
• Calculate the difference between the simulation results and the results taken from the first step. The differences are visualized, in an image format output file, so that the differences can be spotted at once and located on the image.
• Run the inverse DWT in software, given as input the results of the simulation and reconstruct the input image.
• Calculate the Peak Signal to Noise Ratio (PSNR) between the original image and the reconstructed image. Should be Infinity or a large number (>50dB).

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench that instantiates:
  • Example design
  • Clock generator
  • File I/O interface that reads image data from a file and writes the results to another file
  • Executable that converts an image to the input format needed for the testbench
  • Executable that converts the simulation results and applies on them the inverse DWT
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including architectural overview, user's guide, detailed specifications and a system integration guide
• Design Support