HomeSolutionsIPMultimedia

JPEG2K_D JPEG 2000 Decoder Core

Description | Symbol | Features | Applications | Block Diagram | Functional Description | Implementation Results | Core Modifications | Support | Verification | Deliverables

The JPEG2K_D provides flexible, efficient, high-performance image decompression by implementing the computationally intensive parts of the ISO/IEC 15444-1 JPEG2000 standard.

Synthesis factors control image size, DWT filter type or entropy encoder quantity. Programmable settings such as block size and number of 2D-DWT levels allow speed/area/power tradeoffs. Flexible interfaces and broad format support simplify integration.

Developed for easy reuse with ASICs or FPGAs, the core requires just 100K ASIC gates.

Symbol

Features

• ISO/IEC 15444-1 JPEG 2000 Image Coding System compliance
• Support for both lossless and lossy decompression of 8 up to 12-bit component data
• Configuration options allow tunable processing rate: default provides 10 Mpixels/sec lossless and considerably higher rates lossy decompression
• Programmable JPEG2000 Options:
  • 2D-DWT filter type (5/3 or 9/7)
  • Number of 2D-DWT levels
  • De-Quantization tables
  • Entropy-coding switches (reset, restart, causal, segmark)
  • Image format (pixel depth, image/tile size, number of components, sub-sampling factors)
  • Code-block size (64x64 or 32x32)
• Tunable architecture during synthesis:
  • Configurable 2D-DWT filter type (5/3 or 9/7 or both)
  • Configurable 2D-DWT data-path accuracy
  • Configurable number of Entropy Decoding Units
  • Configurable maximum image/tile sizes
• Flexible Interfaces
  • 16-bit synchronous SRAM-style host IF
  • Polling registers and/or interrupt generation
  • Pixel can be extracted either through the pixel-out IF or through the host IF
• Fully synchronous design

Applications

The JPEG2K_D core can be utilized for a variety of multimedia uses including:

• Digital still cameras
• Networked video and image distribution systems
• Wireless video and image distribution systems
• Digital CCTV and surveillance systems
• Image/Video editing systems
• SDTV

Block Diagram

Functional Description

The JPEG2K_D is designed to cooperate with a stream parser. The external stream parser is responsible for collect-ing the attributes and code- segment(s) of each code-block of each tile-component and feeding them to the core. The core is “color-blind” and “tile-blind”; this means that it treats tile-components as separate single-component images. An ex-ception to this behavior is the quantization tables, which can be either re-programmed before a new tile-component is fed to the core, or can be programmed once for each image. In the latter case, the quantization table to be used is identified via the component-field of the code-block attributes data.

In terms of internal operation, an entropy-decoder engine de-codes the code-segments of a code-block. The decoded bit-planes are stored in the corresponding code-block memory. The synthesizer/de-quantizer converts the bit-planes to coef-ficients, performs inverse quantization and stores the result to the external tile-memory. Once all code-blocks of a tile-component have been decoded, the DWT engine takes over and performs the (5/3 or the 9/7) two-dimensional inverse discrete wavelet transform.

The input/output data can be fed/read to/from the core either using the dedicated interfaces (Stream-In/Pixel-Out), or through the host interface.

The memory requirements of the core are summarized in the following table:

Memory requirements of the core summarized

Implementation Results

JPEG2K_D reference designs have been evaluated in a va-riety of technologies. The default configuration of the core (using three entropy-decoding engines and both 5/3 and 9/7 DWT filters) fits for example a Xilinx VirtexII-1000 or higher FPGA. Other FPGA vendor devices as well as ASIC implementations are feasible, under the condition that they provide enough logic cells and internal memory space. Results for a representtive ASIC implementation follow.

Representtive ASIC implementation results

Core Modifications

Customization services are available to modify the core’s interfaces to satisfy specific customer needs (e.g. the host interface might be made AMBA-compatible).

The necessary stream parser is not delivered with the core because a universal version supporting all the posible progression orders and multiple significance layers forseen by the standard would lead to a hardware inefficient implementation Custom development of a stream-parser for a specific progression order and a single or no- significance layers can be completed upon request in a very short time.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide