Most of the image/video compression standards (JPEG, MPEGx, H.261, H.263, DV etc) are based on the Discrete Cosine Transform (DCT). The IDCT-DV core implements the 2D Inverse Discrete Cosine Transform (2D- IDCT) on an 8x8 of DCT coefficients for both 8-8 and 2-4-8 modes of operation. The 2-4-8 IDCT mode associated with the digital video cassette (DVC) standard and the more widely used 8-8 IDCT associated with other formats of compressed video. DV formerly DVC is a new digital recording format being backed by the main manufacturers such as Sony, Philips, Thomson, Hitachi, and Matsushita Panasonic. It was the first digital recording format in the reach of consumer markets. Its main advantage is that it lends itself easily to video editing operations. DV uses a 5:1 DCT-based compression scheme at a fixed rate of 25Mbps. Depending on whether the difference between two fields is small or large, the encoder adaptively decides whether to compress picture fields separately (small difference) or combine two fields into a single compression block (large difference). Therefore, in a certain sense, DV coding can be thought of as a standard that lies in the midway between Motion JPEG and MPEG. Being carefully designed and rigorously verified, the IDCT-DV is a reliable and easy-to-integrate core. Ease of integration is served by a complete verification environment, and additional aids for system on chip simulation, such as a software bit-accurate model.
Features
Ease of integration
High clock speed
Low gate count
One IDCT operation per clock cycle
Low latency
Programmable mode of operation (8-8 or 2-4-8)
Design Quality
Registered input and outputs
Robust verification
Scan-ready design
Applications
The IDCT-DV core can be used for a variety of multimedia applications including:
Office automation equipment (Multifunction printers, digital copiers etc)
Digital cameras & camcorders
Video production, video conference
Display-projection systems
Surveillance systems
Block Diagram
Functional Description
The IDCT-DV receives the weighted DCT coefficients in col-umn-by-column order via the IDCT-In interface and outputs image samples in row-by-row raster scan order via its IDCT-Out interface. The core’s operation can be controlled via a single input signal, the idct_format. The idct_format masks the input block of DCT coefficients: if it is high the input block is assumed to be 8-8 DCT coefficients, while if it is low the input block is assumed to be 2-4-8 DCT coefficients.
Implementation Results
IDCT-DV reference designs have been evaluated in a variety of technologies. The following are sample ASIC technology pre-layout results obtained after area optimization during synthesis, as reported from the synthesis tool and silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
ASIC Technology
Logic Eq. Gates
Frequency
(MHz)
Memory
UMC 0.18μ process
21,797 gates
200
960 bits
TSMC 0.09μ process
21,018 gates
300
960 bits
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements. Being embedded in numerous of products, the core is silicon proven in both FPGA and ASIC technologies.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide
