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HUFFE JPEG Huffman Encoder Core

Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables

The JPEG Huffman Encoder core is a high performance solution for image and video compression applications. The core implements the Huffman entropy encoder part of the baseline ISO/IEC 10918-1 JPEG standard and it is fully compliant with it.

Features

• Fully baseline ISO/IEC 10918-1 JPEG compliance
• 4 fully programmable internal Huffman Tables (2 AC - 2 DC)
• Robust tables programming interface
  • Programmed through Lists Of Codes and Sets Of Values as these are defined in the JPEG standard
• Supports Restart Markers
• Supports output byte alignment and signaling
• Fully synchronous design without any internal tristates
• Fully stallable
• Single cycle processing
• Low memory needs: 4.5 Kbit
• High performance: Sustained rate of 50 – 150 MSamples/sec on FPGAs
• Synthesizes to approximately 6,000 gates into a 0.18 μm process

Applications

The HUFFE can be utilized for a variety of multimedia applications including:

• JPEG Encoder
• Scanners
• Digital Cameras & Camcorders
• Surveillance systems
• Still Image & Video Coding
• Medical Imaging

Symbol Diagram

Block Diagram

Functional Description

The core has two modes of operation:

Tables Programming

Special care has been taken in order to make tables pro-gramming simple and transparent to the user of the core. As a result of this effort a very robust programming scheme has been achieved. The core is programmed through the Tables I/F by just writing to the p_din port two lists for each Huffman table:

• The List Of Codes list, that is a 16-byte list denoting num-ber of codewords for codeword lengths 1 to 16
• The Set Of Values list, that is a variable length byte list containing the Symbols that correspond to codewords defined with previous list

These two lists are exactly the lists defined in ISO/IEC 10918-1 JPEG standard for Huffman tables programming.

The core can accept these two lists without any clock cycle gap, and furthermore no cycle gap is either needed between pairs of lists for programming all four tables.

Entropy Coding

Source data are input to the Huffman encoder through the ‘Data In’ interface. The source data to be entropy coded are the Run-Amplitude pairs and the End Of Block (eob) signal-ing. Selection of the huffman tables that will be used for encoding the input data is signaled with the dc_ac and lum_chr pins. Input data are masked with the valid pin. The symbol generator categorizes amplitude and considering also the type of data (AC or DC) and the eob signal it generates the huffman symbol to be encoded. This symbol is used to access the Huffman tables and read from them the codeword that refers to this symbol. Assembler accepts the amplitude, transforms it to the suitable binary representation defined in JPEG standard, truncates it according to its category, appends it to the codeword and stores this variable length outcome to the output FIFO. Once enough bits have been packed to the FIFO to produce a valid 32-bit output the core puts them to the h_out port and masks them with the h_out_valid signal.

To support restart markers insertion to the output stream, output FIFO can be flushed with reference to an input sample masked with the restart (or flush_in) signal. Once the bits produced from entropy coding of the restart (or flush_in) masked input are packed to the FIFO, the core adds (stuffs) with ‘1’s the rest non-valid bits of the FIFO and puts FIFO contents to the flush_out port. The signal flush_out_valid is raised to validate this operation and the 2-bit flush_byte port is updated with the value that points the last valid byte in the 32-bit output. Following a flush operation and before the next bits are packed to the FIFO the FIFO pointers are cleared, so that the contents of the next valid output double word begin from these bits.

Implementation Results

HUFFE reference designs have been evaluated in a variety of technologies. The following are sample ASIC results:

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

Large sets of test vectors have been applied to the core to verify its accurate operation. These test vectors were pro-duced by using a prototype JPEG encoder written in C as a generator for the Huffman Encoder input data. After feeding the test data to the core the outputs were compared to that of the prototype.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including example design, data I/O modules for test vectors
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide