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HUFFD JPEG Huffman Decoder Core

Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Core Modifications | Support | Verification | Deliverables

This core implements the Huffman entropy decoder part of the baseline ISO/IEC 10918-1 JPEG standard.

It is capable of decoding an incoming JPEG data stream and producing one output symbol per cycle. The output is the RUN/SIZE code as well as the amplitude of the non-zero coefficient.

The core’s Huffman decoding tables are fully user programmable, and the core comprises two DC and two AC internal tables.

Features

• Huffman Decoder – 100% baseline ISO/IEC 10918-1 JPEG compliance
• Two AC and two DC Internal Huffman Tables are fully and easily programmable:
  the core accepts just the Lists Of Codes and Sets Of Values, as these are defined in ISO/IEC 10918-1
• Auto DC extraction mode
• End Of Block signaling
• Supports Restart Markers
• One Symbol extraction per cycle

Applications

The HUFFD can be utilized in a variety of multimedia applications including:

• JPEG Decoder
• Still Image Coding
• Video Coding
• Printers
• Digital Cameras
• Medical Imaging

Symbol Diagram

Block Diagram

Functional Description

The core has two distinguished modes of operation:

• Tables Programming
• Run (Data decode)

Tables Programming

The core enters the programming mode of the internal Huffman tables when Run_Program is low. While in this mode core accepts the table data, in the form of List Of Codes and Set Of Values as defined in JPEG standard, to the 8 LSB’s of DIN port. Code_Symbol pin selects between these two lists. Distinction of the target table is signaled with the usage of the AC_DC and Lum_Cr pins. The TABLES_I/F block generates additional support data, stored inside the core.

Run Mode – Decoding Data

When Run_Program is high the core operates in the Run-decoding data mode. While in this mode the core asks for 32 bit data to the DIN port by raising the LOAD pin and decodes them according to the programmed tables. The table that is used to decode the data is defined through the Lum_Cr pin and the AC_DC, USE_AC_DC pair of pins. Lum_Cr selects between Luminance and Chrominance tables. When USE_AC_DC is low the first coefficient of each new block is treated as DC coefficient and the rest 63 as AC coefficients (auto DC mode). With USE_AC_DC set to high the AC_DC pin is used instead to select between AC or DC tables. Lum_Cr, AC_DC, and USE_AC_DC inputs are sampled at the end of a block and they refer to the whole next block to be decoded.

Core outputs the RUN/SIZE code and the amplitude of the non-zero coefficient in two’s complement representation. Output data are masked with the active high DataValid pin.

When the core detects that the “EOB”(0/0) symbol is decoded, or after 64 coefficients have been decoded, the EOB signal is raised for one clock cycle.

Implementation Results

HUFFD reference designs have been evaluated in a variety of technologies.

Core Modifications

The core can be customized to use external memories for storing the Huffman tables data.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

A behavioral model of a Baseline JPEG decoder has been developed that uses this core for the entropy decoder part. This model is delivered with the core. This JPEG model supports single component, 8-bits sample precision grayscale images, and three component (4:1:1) 24-bit color images (YCbCr).

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Reference C source code (at extra charge)
• Sophisticated HDL Testbench that instantiates:
  • Example design
  • Clock generator
  • Process interfacing design
  • Data I/O modules
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications, architectural overview, user guide, and a system integration guide
• Design support