DCT 2D Forward Discrete Cosine
Transform Core
Description | Features | Applications | Block Diagram | Functional Description | Core Modifications | Implementation Results | Support | Verification | Deliverables
The DCT Core implements the 2D Forward Discrete Cosine Transform (2D-DCT) on an 8x8 block of samples. Hence, it is appropriate for DCT-based image or video CODERS and can be used as a core for JPEG, MPEG1, MPEG2, MPEG4, H.261, and H.263 standards. It is based on the row-column computational architecture.
The DCT is designed for reuse in ASIC and FPGA implementations. The design is fully synchronous with positive edge clocking and no internal tri-state buffers. It offers high performance, while maintaining a low gate count, and can be used in any multimedia, digital video and digital printing applications.
Features
- High clock speed
- Low gate count
- 8x8 DCT block size
- Continuous one symbol per clock cycle
- 8 bpp inputs, 11-bit inputs, 12-bit cosine coefficients and 15-bit internal computations pre-cision
- No internal RAM requirements
- Internal zero-level shifting on input samples
- Low latency (82 cycles)
Applications
The DCT core is a typical building block for image processing applications and can be utilized for a variety of multimedia applications including:
- Image compression
- Digital printing
- Desktop video editing
- Digital still cameras
- Various progressive image transmission (PIT) systems such as:
- Teleconferencing
- Medical diagnostic imaging
- Security services
Block Diagram
Functional Description
The DCT is a transform that converts a signal into its constituent frequency components as represented by a set of coefficients. For an image, this transform is performed on a 2 dimensional array of samples, resulting in a 2 dimensional ar-ray of coefficients. The data input into the core and output from the core takes place as a block of 8x8 samples.
The DCT core can perform Forward Discrete Cosine Trans-form (DCT) on an 8x8 block of samples. The mathematical definition for the DCT is given below.
where  are the input image samples,  are the output DCT co-efficients,  for  and  otherwise and N=8.
The DCT transformation is implemented using the row/column algorithm (due to separarability property of the above equations), i.e. DCT transformation is implemented as a two-stage process. The two-stage process performs the transform as two separate one-dimensional transforms, with the intermediate results being stored in a small transpose memory (dual-port RAM).
Figure 1 is a block diagram of the core, showing the main in-terfaces and functional blocks. The basic building blocks of the core are described in the following sections.
Stage 1
This processing stage comprises a set of multiplier-accumulator units as well as a Cosine lookup table for re-spective DCT computations. The input to this stage is the 8 bit data DIN from the I/O port. The output from this process-ing stage is a word of 15 bits length and passed onto the transpose memory.
Stage 2
This processing stage comprises a set of multiplier-accumulator units as well as a Cosine lookup table for re-spective DCT computations. The input to this stage is the data stored in the transpose memory by stage 1. This stage, similar to stage1, performs a 1-D DCT and provides the final 11 bit output coefficient at DOUT port.
Control Unit
This is the control unit for the DCT transformation. It receives all input control signals (RESET, START) and generates: a) all the internal control signals for each stage and, b) the out-put control signals for communication (BUSY, READY, DATA_AV) and c) the control signals for the communication with the external transpose memory.
Transpose Memory
The core requires an externally connected dual-port RAM of 64 words in order to operate correctly. This memory is used to store DCT intermediate results. The core will use one port as write only and the other port as read only. The two ports must be able to be independently addressed. Both the write and read ports will be accessed by the core synchronously, with a clock synchronous to the DCT core clock.
Core Modifications
The DCT core can be easily customized to meet your area/throughput constraints. Essentially the core can be modified as follows: a) a dual-port RAM can be included within the core for technologies that provide such memory blocks; b) if the image block is stored in a single port mem-ory, then the IP needs only one DCT_block that implements the row/column DCT algorithm (area saving because only one stage is needed but half the throughput); c) the blocks size (N=8 or 16) input/output, cosine and internal precisions are configurable. Please contact CAST directly for any re-quired modifications.
Implementation Results
DCT reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Bit Accurate BAM Model
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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