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DCT_FI 2D Forward/Inverse Discrete

Cosine Transform Core

The DCT_FI Core implements the 2D Forward and Inverse Discrete Cosine Transform (2D-DCT/IDCT) on an 8 x 8 or 16 x 16 block of samples. Hence, it is appropriate for DCT-based image or video encoder/decoders (CODECs) and can be used as a hard-ware implementation for the JPEG, MPEG1, MPEG2, MPEG4, H.261, and H.263 standards. It is based on the row-column computational architecture.

The DCT_FI is designed for reuse in ASIC and FPGA implementations. The design is fully synchronous with positive edge clocking and no internal tri-state buffers, and scan insertion is straightforward. The DCT_FI offers high performance while maintaining a low gate count.

Features

High clock speed and low gate count.
DCT and IDCT, both supported on 8 x 8 (N=8) or 16 x 16 (N=16) block of samples.
One clock-cycle per DCT and IDCT operations.
User-defined DCT and IDCT input/output precisions.
No internal RAM requirements.
Interfaces with external connected dual port RAMs of size N2.
Extensive parameterization enables fine tuning of various core features, including:
- Block Type that is used for DCT/IDCT (8 x 8 or 16 x 16).
- Bit-Widths (input image, cosine coefficients, internal data path, input/output precision).
- Forward/Inverse Transform (both or each one of them separately).
- Normalization or not of input/ output samples (zero shifting over the middle of pixel range).
Fully synchronous with asynchronous reset and without internal tri-state buffers.

Applications

The DCT_FI can be used in a variety of multimedia and image processing applications, including:

Digital video
Digital printing
Digital still cameras
Progressive image transmission (PIT) systems such as:
- Teleconferencing systems
- Medical diagnostic imaging instruments
- Security services

Block Diagram

Functional Description

The DCT_FI Core can perform both Discrete Cosine Trans-form (DCT) and its inverse (IDCT) on an 8 x 8 (or 16 x 16) block of samples (from now on, N x N is the block size for DCT/IDCT). The mathematical definition for the DCT and IDCT are shown below.

where for and other-wise.

To operate the DCT/IDCT, the core must be connected to an N x N external, connected, Dual-Port RAM. Due to the separarability property of the above equations, the DCT/IDCT transformation is implemented using the row/coumn algo-rithm as a two-stage process. The two-stage process performs the transform as two separate, one-dimensional transforms, in which the intermediate results are stored in a small transpose memory (dual-port RAM).

The Block Diagram shows the main interfaces and functional blocks. The basic building blocks of the core are described in the following sections.

Stage 1

This processing stage comprises a set of multiplier-accumulator units and a Cosine lookup table for the respec-tive DCT/IDCT computations. The input to this stage is the data DIN from the I/O port. The output from this processing stage is a 15-bit word passed onto the transpose memory.

Stage 2

This processing stage comprises a set of multiplier-accumulator units and a Cosine lookup table for the respec-tive DCT/IDCT computations. The input to this stage is the data stored in the transpose memory by Stage 1. Stage 2 is similar to Stage 1 in that it performs a 1D DCT and provides the final 11-bit output at the DOUT port during DCT or the 8-bit output during IDCT mode.

Control Unit

This is the control unit for the DCT/IDCT transformation. It receives all input control signals (RESET, START, FORWARD) and generates all the internal control signals for each stage, the output control signals for communication (BUSY, READY, DATA_AV) and the control signals for the communication with the external transpose memory.

Transpose Memory

The core requires an externally connected dual-port RAM of 64 words to operate correctly. This memory stores DCT and IDCT intermediate results. The core will use one port as write only and the other port as read only. The two ports must be able to be independently addressed. Both the write and read ports will be accessed by the core synchronously, with a clock synchronous to the DCT_FI core clock.

Implementation Results

DCT_FI reference designs have been evaluated in a variety of technologies.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The correct operation of the DCT_FI core was verified for all possible sets of parameters as follows: A large number of im-ages were fed to the core, which sequentially implemented the forward and inverse 2D-DCT. PSNR measurements among the reconstructed and original images were per-formed. Furthermore, the outputs (decomposed or synthesized image) of the HDL core have been binary com-pared to the outputs of the reference software.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Bit-accurate C source model (BAM)
Sophisticated HDL Testbench including including
- design example with forward and inverse cores;
- external image, dual-port RAMs, and a control signals generator;
- process comparing original and reconstructed images and producing the PSNR value between them; and
- everything else needed to test the core.
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide

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