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CSC Color Space Conversion Core

Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables

The CSC core is a compact, high-performance, highly flexible color space conversion core, which can be used to convert from any color space with 3 color channels, to any color space with 3 color channels (e.g. RGB to YCrCb, YCrCb to RGB).

Different color space models are used for different purposes in video/image processing systems. For example computer monitors typically receive frames in the RGB color space, while in order to be compressed frames are typically converted to a luminance – chrominance color space (e.g. YCrCb). So, color space conversion is often necessary when transferring data between devices that use different color space models.

The CSC is a small, fast design that implements a single conversion function. Two other CSC family cores are also available:

• The CSC-P Programmable version can convert from any color space with three color channels to any other color space with three color channels (download CSC-P PDF datasheet). It processes all three channels in parallel.
• The CSC-PT Programmable, Time-Multiplexed IO version can also handle any color space conversion, but it multiplexes the three color channels on a single bus (download the CSC-PT PDF datasheet). The CSC-PT is thus smaller, but the CSC-P has three times the throughout of the CSC-PT.

The CSC cores area testable, microcode-free designs developed for reuse in ASICs and FPGAs.

Features

Synthesis-time configurable conversion function

• Computer R’G’B’ to Y’CrCb
• Y’CrCb to Computer R’G’B’
• Studio R’G’B’ to Y’CrCb
• Y’CrCb to Studio R’G’B’
• Computer R’G’B’ to Y’UV
• Y’UV to Computer R’G’B’
• User specified

Synthesis-time “tunable” architecture

• Configurable number of bits per input and output sample
• Configurable number of bits per transformation-table coefficient
• Configurable data-path accuracy
• Pipelined or non-pipelined multipliers
• Selectable synchronous and/or asynchronous reset
• Configurable sensitivity level for all control signals

Optional Supplementary Functionality

• Gamma correction removal
• Quantization/Dithering
• Up or Down -Sampling

Design Quality

• Continuous one symbol per clock cycle processing
• High clock rate
• Low gate count (<3k eq. gates)
• Low Latency (5 cycles)
• Fully scan insertable design
• Registered input and outputs
• Solid verification plan
• ANSI-C Bit-accurate model

Applications

The CSC can be utilized for a variety of multimedia applications including:

• Image Grabbers
• Display Systems
• Image/Video processing applications
• Image/Video compression / decompression systems
  

Symbol Diagram

Block Diagram

Functional Description

The CSC core performs the ABC to XYZ color space conversion. The CSC core uses the following equation in order to convert data from one color space to another:

After the conversion of a triplet of input samples, the core performs rounding and saturation control before outputting the converted triplet of samples.

Implementation Results

CSC Implementation Results

The CSC core can be implemented either in FPGA devices or ASIC technologies. The following table provides indicative implementation data in terms of area and clock frequency for some FPGA devices and ASIC technologies. The provided indicative implementation data are acquired for the pipelined version of the core implementing Y’CrCb to computer R’G’B’ conversion with input and output bit-width of 8 bits, conversion coefficients bit-width of 10 bits, and the data-path accuracy of 12 bits. Other conversions perform slightly faster, and occupy approximately the same area.

It is noted that area requirements are reduced for the non-pipelined version of the core, and if the enable and clear ports are not used (i.e. they are hardwired before synthesis). For example, for the same configuration described above but with hardwiring the enable and clear ports, the core occupies 22% less area (4157 eq. gates).

CSC-P Implementation Results

The CSC-P core can be implemented either in FPGA devices or ASIC technologies. The following tables provide indicative implementation data in terms of area and clock frequency for some FPGA devices and ASIC technologies. The provided indicative implementation data are acquired after setting the input and output bit-width to 8 bits, the conversion coefficients bit-width to 10 bits, and the data-path accuracy to 12 bits.

CSC-PT Implementation Results

The CSC-PT core can be implemented either in FPGA de-vices or ASIC technologies. The following tables provide indicative implementation data in terms of area and clock frequency for some FPGA devices and ASIC technologies. The provided indicative implementation data are acquired after setting the Input and output bit-width to 8 bits, the conversion coefficients bit-width to 10 bits, and the data-path accuracy to 12 bit.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• An example chip implementation, which uses the CSC in a sample system
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide