The R80515 is a fast, single-chip, 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of 8 times faster.
The R80515 provides software and hardware interrupts, extra timer features, power management, and Infineon peripherals support. On-chip debugging is an option.
The microcode-free, strictly synchronous design was developed for reuse in ASICs and FPGAs. Scan insertion is straightforward.
Features
Control Unit
8-bit Instruction decoder
Reduced instruction cycle time up to 12 times
8-bit Arithmetic-Logic Unit
Multiplication-Division Unit
16 x 16 bit multiplication
32 / 16 bit and 16 / 16 bit division
32 bit L/R shifting and normalization
32-bit Input/Output ports
Four 8-bit I/O ports
Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051
Three 16-bit Timer/Counters
Compare/Capture Unit
Four 16-bit compare registers used for pulse width modulation
Four external capture inputs used for pulse width measuring
16-bit Reload register used for pulse generation
Two Serial Peripheral Interfaces in full duplex mode
Synch mode, fixed baud rate, Serial 0 only
8-bit UART mode, variable baud rate
9-bit UART mode, fixed baud rate, Serial 0 only
9-bit UART mode, fixed & variable baud rate
Additional baud rate generator for Serial 0
Four priority/thirteen sources Interrupt Controller
15 bit Programmable Watchdog Timer
Internal Data Memory interface
Can address up to 256 bytes of Read/Write Data Memory Space
External Memory interface
Can address up to 64 KB of External Program Memory
Can address up to 64 KB of External Data Memory
De-multiplexed Address/Data Bus to allow easy con-nection to memories
Variable length MOVX to access fast/slow RAM/ or peripherals
Variable length code fetch and MOVC to access fast/slow program memory
Dual data pointer for fast data block transfer
Special Function Registers interface - Services up to 74 External SFRs
The R80515 can be utilized for a variety of applications including:
Embedded microcontroller systems
Data computation and transfer
Communication systems
Professional audio and video
Symbol Diagram
Block Diagram
Performance
The architecture eliminates redundant bus states and im-plements parallel execution of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. The R80515 uses 1 clock per cycle. This leads to performance improvement of rate 8x (in terms of MIPS) with respect to the Intel device working with the same clock frequency (the original 8051 had a 12-clock architecture. A machine cycle needed 12 clocks and most instructions were either one or two machine cycles. Thus except for the MUL and DIV instructions, the 8051 used either 12 or 24 clocks for each instruction. Furthermore, each cycle in the 8051 used two memory fetches. In many cases the second fetch was dummy, and extra clocks were wasted).
The table below illustrates the speed advantage of the R80515 over the standard 8051. A speed advantage of 12 means that the R80515 performs the same instruction twelve times faster that the R8051.
Speed advantage
Number of instructions
Number of opcodes
24
1
1
12
27
83
9.6
2
2
8
16
38
6
44
89
4.8
1
2
4
18
31
3
2
9
Average: 8.0
Sum: 111
Sum: 255
The average of speed advantage is 8x, however, the actual speed improvement observed in any system will depend on the instruction mix.
Implementation Results
R80515 reference designs have been evaluated in a variety of technologies. The following are sample ASIC results:
ASIC Technology
Approx.
Area
Frequency
(MHz)
Optimized
For:
TSMC 0.18
18,883 gates
303
speed
TSMC 0.18
14,611 gates
151
area
TSMC 0.25
20,155 gates
250
speed
TSMC 0.25
14,223 gates
125
area
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The R80515 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C31 chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Vectors for testing the core
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide
