CZ80PSC 8-bit Intelligent Peripherals
Controller Core
Description | Features | Applications | Symbol | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The CZ80PSC core implements an 8-bit microprocessor CZ80CPU integrated with CTC, SIO, PIO and WDT units. This intelligent peripheral controller is well suited for a broad range of applications ranging from error correcting modems to enhancement/cost reductions of existing hardware using Z80-based discrete peripherals.
The CZ80PSC is designed to run at frequencies up to 68 MHz on a typical 0.35-micron process and it uses less than 26K gates depending on the technology. The CZ80PSC is a technology independent design that can be implemented in a variety of process technologies.
Features
8-bit Microprocessor Unit
- 8- bit Control Processor Unit
- 8/16-bit Arithmetic-Logic Unit
- Interrupt Controller with maskable and non maskable interrupts
- 16-bit address bus capable of direct access of 64kB of memory space
Serial Input/Output Unit
- Two independent full – duplex channels
- Speed rate up to 2M bits/second with 10MHz clock
- Asynchronous and synchronous protocols
Counter-Timer Circuit Unit
- Four independently programmable counter/timer channels
- Readable down-counters
- Selectable 16 or 256 prescalers
- Selectable positive or negative trigger for timer
Parallel Input/Output Unit
- Two ports with interrupt-driven handshake
- Four programmable operating modes
Watchdog Timer
- Programmable 23-bit counter
Applications
The CZ80PSC is well suited for a broad range of applications. Typical applications include:
- error correcting modems
- enhancement/cost reductions of existing hardware using Z80-based discrete peripherals
Symbol Diagram
Block Diagram
Functional Description
Functionally, the on-chip SIO, CTC, PIO and the CPU are the same as the separate cores. Therefore, for detailed de-scription of each individual unit, refer to the Specification of each separate product. The following subsections describe each individual functional unit of the CZ80PSC.
CPU – Control Processor Unit
The CPU provides all the capabilities of the CZ80CPU. This allows 100% software compatibility with existing Z80 software.
CTC - Counter/Timer Logic Unit
This logic unit provides the user with four individual 8-bit Counter/Timer Channels that are compatible with the CZ80CTC. The Counter/Timer can be programmed by the CPU for a broad range of counting and timing applications. Typical applications include event counting, interrupt and interval counting, and serial baud rate clock generation.
Each of the Counter/Timer Channels designated Channels 0-3, have an 8-bit prescaler (when used in timer mode) and its own 8-bit counter to provide a wide range of count reso-lution. Each of the channels have their own Clock/Trigger input to quantify the counting process and an output to in-dicate zero crossing/timeout conditions. With only one interrupt vector programmed into the logic unit, each chan-nel can generate a unique interrupt vector in response to the interrupt acknowledge cycle.
SIO - Serial I/O Logic Unit
This logic unit provides the user with two separate multipro-tocol serial I/O channels that are completely compatible with the CZ80SIO. Their basic functions as serial-to-parallel and parallel-to-serial converters can be programmed by a CPU for a broad range of serial communications applica-tions. Each channel, designated Channel A and Channel B, is capable of supporting all common asynchronous and synchronous protocols (Monosync, Bisync, and SDLC/HDLC, byte or oriented).
PIO - Parallel I/O Logic Unit
This logic unit provides interface between peripheral de-vices and a CPU through the use of two 8-bit parallel ports. The CPU configures the logic to interface to a wide range of peripheral devices with no external logic. Typical devices that are compatible with this interface are keyboards, print-ers, A/D and D/A converters, and EPROM/PAL programmers.
The parallel ports (designated Port A and Port B) are 8-bit wide and completely compatible with the CZ80PIO. These two ports have four modes of operation: input, output, bidi-rectional, or bit control mode. Each port has two handshake signals (rdy and stb_n) which are used to control data transfers. The rdy (ready) indicates that the port is ready for data transfer while stb_n (strobe) is an input to the port that indicates when data transfer has occured. Each of the ports can be programmed to interrupt the CPU upon the occur-rence of specified status conditions, and generate unique interrupt vectors when the CPU responds.
WDT - Watch-Dog Timer Logic Unit
This logic unit has been superintegrated into the PSC. It detects the operation error, caused by the program run-away, and returns to normal operation.
When the WDT is used, the '0' level signal is output from the wdt_out_n pin after a duration of time specified in the WDT control registers. The output pulse width is one of the following, depending on the wdt_out_n pin connection:
- the wdt_out_n is connected to the reset_n pin: the '0' level is pulsed for 5 system clock cycles.
- the wdt_out_n is connected to a pin other then the reset_n pin: the '0' level is kept until the Watch-Dog Timer is cleared by software, or reset by reset_n pin.
Implementation Results
CZ80PSC reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The CZ80PSC core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Zilog chips, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- An example chip implementation, which uses the CZ80PSC in a sample system
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide
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