C80186TX 16-bit Microprocessor Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Implementation Results | Support | Verification | Deliverables
The C80186TX is a single-chip, high-performance 16-bit processor core. It implements the same widely known instruction set as the 80c86 and the 80c186 processors.
The C80186TX is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with a synchronous reset and no internal tri-states.
Features
- Control Unit
- 9-level deep and byte wide instruction queue
- Reduced instruction cycle time up to 12 times
- Arithmetic-Logic Unit
- 16-bit arithmetic and logical operations
- 16 x 16-bit multiplication and 32 / 16-bit division
- Memory interface
- 20-bit addressing; non-multiplexed address bus
- True asynchronous bus interface
- 1MB memory space divided into 64KB segments
- Single cycle memory access, to instruction and data
- 64-KB I/O space
- Chip Select Unit
- 6 chip select outputs for use with memory devices
- 6 select lines for external peripheral devices in memory or IO space
- Peripheral Control Block
- 256 bytes of control memory, mapped into memory or I/O space
- All mapped registers are 16-bit wide
- Direct Memory Access
- 4 separate fully functional DMA channels
- Direct connection to UART device and Timer2
- External transfer initiation by DRQn pins
- Advanced Power Management Unit
- Three 16-bit Timer/Counters
- 16-bit programmable Watchdog timer
- Two Serial Peripheral Interfaces in full duplex mode
- Programmable Interrupt Controller
- 7 external interrupt lines, including NMI
- 9 internal interrupts from peripherals
- Refresh control unit
- DRAM controller
- Controls up to two banks of memory
- Zero wait state operation with DRAM-50 memory at 40MHz
- Pulse Width Demodulation feature
- Math coprocessor interface - 80C187 compatible
Applications
The C80186TX can be utilized for a variety of processor applications.
Symbol Diagram
Block Diagram
Implementation Results
C80186TX reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C80186TX core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C186EB chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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