The C56000 is a single-chip, 24-bit, fixed-point digital signal processor. The efficient modified Harvard architecture provides high precision and performance using independent X/Y memory accesses. The C56000 implements the same instruction set as the industry standard DSP56002, and also provides the same peripherals and interrupts.
The C56000 is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with synchronous reset, no internal tri-states.
Features
Control Unit
66 instructions set
24-bit instruction decoding
3-stage instruction pipelining
Most instructions executed in two cycles (all arithmetical instructions)
Repeat instructions for efficient use of program space and enhanced execution
Hardware loops support
16-level deep hardware stack
Most arithmetic instructions with parallel move
Data Arithmetic Logic Unit
Four 24-bit input registers
Two 48-bit accumulator registers
Two 8-bit accumulator extension registers
Accumulator shifter
Two data bus shifter/limiter circuits
24 x 24 parallel multiplier
56-bit arithmetic and logic operations
Single-cycle Multiply-and-Accumulate with rounding instructions
Address Generation Unit
Eight sets of three 16-bit registers : address, offset and modifier registers
Direct, indirect, immediate addressing modes
Varied indirect addressing modes with linear, modulo and reverse-carry arithmetic
Two 16-bit addresses calculation in every instruction cycle
Memory organization
Program and X/Y Data memory spaces
Configurable program and data memory map
512 words of internal program RAM
256 words of RAM and 256 words of ROM for both X and Y internal data memory spaces (for user-defined tables, e.g. A-Law, sine-wave table)
Up to 64K words of external space for each program, X and Y memories
Wait states for interfacing slower off-chip devices (and internal wait-state generator)
I/O ports
24 General-purpose I/O pins
Serial Communication Interface (SCI)
Synchronous Serial Interface (SSI)
Host Interface (HI)
24-bit timer
External event counter
External pulse width/period measurement
Timer
Pulse generation
Applications
The C56000 can be utilized for a variety of digital signal processing applications.
Symbol Diagram
Block Diagram
Performance
The C56000 implements modified Harvard-type architecture to maximize processing power by maintaining separate two -data and one -program bus for full-speed execution. Two clock cycle arithmetical instructions, three on-chip RAM blocks, Address Generation Unit with twenty four dedicated registers, two full-duplex serial interfaces, a hardware timer and Host Interface make the processor appropriate for data-intensive signal processing.
Each of execution units (Address Generation Unit, Program Control Unit, Arithmetic-Logic Unit), memory, and peripherals operate independently and in parallel with the other units using a sophisticated bus system. Instruction pre-fetch, 24-bit x 24-bit multiplication, 56-bit addition, two data moves and two address-pointer updates can be executed in a single instruction cycle. The Address Generation Unit uses one of three types of arithmetic (linear, modulo, or reverse-carry).
Instruction flow consists of three pipeline stages, essentially invisible to the user. The pre-fetch, decode and execute operations are independent, that allows instruction executions to overlap.
The processor can repeat one instruction or the block of instructions by given number of times. Nested loops are also possible which is very useful in DSP algorithms.
Implementation Results
C56000 reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C56000 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Motorola DSP56002 chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Wrapper for pin compatible replacement
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide
