C49402 16-bit Microprocessor Slice Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The C49402 16-bit microprocessor slice core is a cascadable ALU intended for use in CPUs, peripheral controllers, and programmable microprocessors. The core includes a dual port RAM, ALU, shifter, register, decoding and multiplexer. The microinstructions of the C49402 allow for easy modeling of various microcontrollers.
Applications
The C49402 core is used where simple micro-programmable controllers are required.
Features
- Eight function ALU
- Expandable – Any number of devices can be connected for wider bus structures
- Support for all original 2901 source, function and destination codes
- Additional destination codes for performance improvement allowing Direct (external) data to be directly loaded into register file and Q register
- 64-word register file with Input Shifter
- Functionality based on the IDT and Cypress 49C402
Symbol Diagram
Block Diagram
Functional Description
The C49402 core is partitioned into sections as shown in the block diagram and described below.
Dual Port RAM
The internal memory is a 16-bit by 64 deep Dual Port RAM. It is addressed for writing by the B Port and for reading by both the A and B Ports. The input data is defined by a microinstruction decoded from 4 bits of the 10-bit I Port.
RAM Latch
These latches store the outputs of the Dual Port RAM. They are clocked using the CP input. This eliminates any possible race conditions that could occur while new data is being written into the RAM
Q Register
The Q register is enabled by the internal signal qen, which is generated by the Instruction input (I) and clocked on the rising edge of CP.
ALU
The ALU accepts input from either RAM Port, the Q Register and cascaded inputs from previous stages. It has basic functions including most logic and arithmetic operations including such functions as shifting, adding and subtracting.
ODecode
The Odecode block takes bits 6 – 9 of MicroInstruction Bus and uses them to control the internal output en-ables and selects of the other blocks.
RSDecode
The RSDecode block takes bits 0 – 2 of the MicroIn-struction Bus and uses them to control the 16-bit R and S buses. These buses get loaded with the outputs of the other blocks, routing various results back through the ALU block.
ENGEN
This block takes the select bits for the ram and q regis-ter and decodes the enable pins for the bi-directional RAM and Q bits
Implementation Results
C49402 reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C49402 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was ap-plied to a hardware model which contained the original IDT 49C402 chip, and the results compared with the core’s simu-lation outputs
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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