C29101 16-Bit Microprocessor Slice Core
Description | Applications | Features | Block Diagram | Functional Description | Related Information | Support | Verification | Deliverables
The C29101 16-bit Microprocessor Slice Core (C29101) is a cascadable ALU for use in CPUs, peripheral controllers, and programmable microprocessors. The C29101 in-cludes a dual port RAM, ALU, shifter, register, decoding and multiplexer. The microinstructions of the C29101 allow for easy modeling of various microcontrollers.
Applications
The C29101 core can be utilized in a variety of applications including:
- CPUs
- Peripheral controllers
- Programmable microprocessors
Features
- Independent and simultaneous access to two registers save machine cycles
- Eight function ALU
- Expandable – Any number of devices can be connected for wider bus structures
- Four status flags for Carry, Overflow, Zero, and Negative
- Micro programmable
- Developed in HDL
- Synthesizes to approximately 4,600 gates depending on the technology used
- Functionality based on the Advanced Micro Devices AM29C101
Block Diagram
Functional Description
The C29101 core is partitioned into sections as shown in the figure C29101 16-Bit Microprocessor Slice Block Diagram and described below:
Dual Port RAM
The internal memory is a 16-bit by 16 Dual Port RAM. It is addressed for writing by the B port and for reading by both the A and B ports. The input data is defined by a microin-struction decoded from three bits of the 9-bit I port.
RAM Latch
These latches store the outputs of the Dual Port RAM. They are clocked using the CP input.
Q Register
This section describes the internal register. It is selected us-ing the Instruction input (I) and clocked with the CP input.
MicroInstructions
The I port is internally decoded to define the flow of data to the above sections.
Related Information
AM29C101 16-Bit CMOS Microprocessor Slice Datasheets, April 1987
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C29101 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was ap-plied to a hardware model which contained the original AMD 29101 chip and the results compared with the core’s simula-tion outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Example testbench wrapper for post-route simulation
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
|
