SHA-1 Secure Hash Algorithm
Cryptoprocessor Core
Description | Applications | Features | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Export Permits | Deliverables
This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 160-bit message digest for messages of up to (264 – 1) bits.
Developed for easy reuse in ASIC and FPGA applications, the SHA-1 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option.
Applications
You can use the SHA-1 in a variety of applications, including:
- Electronic Funds Transfer
- Authenticated Electronic data transfer
- Encrypted data storage
Features
- Designed according to the FIPS 180-1 Standard
- Suitable for data authentication applications
- Fully synchronous design
- Also available in VHDL or Verilog
Symbol Diagram
Block Diagram
Functional Description
The SHA-1 algorithm is based on principles similar to those used by Professor Ronald L. Rivest of MIT when designing the MD4 message digest algorithm, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 160-bit (5 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message. A block diagram of the core is shown above.
Timing diagram 1 shows the first message block of 512 bits, comprising sixteen 32-bit words, being clocked into the core. The INIT signal is asserted at the start of each message to initialize the logic for calculating a new message digest. The SHA core is ready to accept data when REQ is asserted.
Each 32-bit word is clocked into the core on the rising edge of CLK when ACK is asserted. After a block of 16 words has been input, REQ is deasserted as the SHA core computes the message digest. After another 65 clock cycles, the message digest for that 16 word block is computed and REQ is asserted again to indicate that more words can be clocked in.
Timing diagram 1 for first message block input
The standard specifies that the maximum number of bits in the message is 264 – 1; therefore, the maximum number of bits in a message is 261 - 1. The core can cope with any number of words up to 261 - 1 being input with the BYTES[1:0] input specifying the number of valid message bytes in the last input word.
Timing diagram 2 shows the last message block being clocked into the core. The LAST signal is asserted when clocking in the last word. At least one pad, and two length words need to be added to the end of the message as part of the SHA calculation.
If the total number of input bytes plus 9 is not a multiple of 64, additional pad bytes are added by the core to calculate the message digest as specified in the standard.
The two length words that contain the bit-length of the original message are also added by the core. Note the three clock cycle de-lay for adding the pad and length words.
Another 66 clocks later, READY is asserted together with the 160-bit message digest output on H0, H1, H2, H3, H4. These outputs remain valid until INIT or RSTN is asserted.
Timing diagram 2 showing last message block input
The core can be asynchronously reset by lowering the RSTN input port. After reset, READY and REQ are deasserted, and H0-H4 are set to 0. The clock enable (EN) signal is asserted high for normal operation. Registers are not updated when EN is forced to 0.
Implementation Results
SHA-1 reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Export Permits
The core is available for export to all countries for non-military applications, except to the following countries:
| Cuba |
Iran |
Iraq |
Libya |
| North Korea |
Sudan |
Syria |
|
For military application only Australia and the United States are allowed. It is the customer’s responsibility to check with relevant authorities regarding the reexport of equipment containing the SHA-1 technology.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- C model for test generation
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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