MODEXP1 Modular Exp. Accelerator for
RSA Core
Description | Applications | Features | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The MODEXP1 implements the most computationally demanding part of the modular exponentiation operation based on the Montgomery algorithm. It can be used in various cryptographic systems, such as RSA encryption or the Diffie-Hellman algorithm.
The core works as a coprocessor and is accessible through a simple interface. Thanks to this simplicity it can be easily ported to almost every processor.
The core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is fully synchronous, without internal three-state buses.
Applications
You can use the MODEXP1 in a variety of applications, including:
- RSA Encryption
- Diffie-Hellman algorithm
- Digital signature
Features
- Uses the Montgomery algorithm
- Relieves the processor from calculating highly complicated and resource consuming algorithm
- Simple interface, can be adjusted to 8-, 16- or 32-bit bus wide systems
- Size of numbers configurable by software at runtime
- Size of supported numbers: 512, 768, 1024, 1536, 2048, 3072, and 4096-bit
- C functions provided for number precomputations
- C functions provided for high-level functionality such as CRT, DPA protection, and regression tests
- Can be used in various cryptographic applications
Symbol Diagram
Block Diagram
Functional Description
As shown in the block diagram, the MODEXP1 core is partitioned into 3 blocks:
Interface
As shown above the interface supports core communication with a host and an external memory. The host interface can be adjusted to 8-, 16- or 32-bit bus systems. The memory interface operates with 5 blocks of synchronous memory. FPGA internal memory blocks can be used as these memory blocks.
Control
This unit supervises internal data flow and correctness of the all the data operations. It also controls optimization of the calculation process.
MAC
The MAC is a multiplication-accumulate unit with some additional features. It provides data operation over small portion of numbers.
Implementation Results
MODEXP1 reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Test pattern generation program
- C support functions
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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