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MD5 Processor Core

Description | Applications | Features | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Export Permits | Deliverables

This core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. It computes a 120-bit message digest for messages of up to (2⁶⁴ – 1) bits.

The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

Applications

You can use the MD5 in a variety of applications, including:

• Electronic funds transfer
• Authenticated electronic data transfers
• Encrypted data storage

Features

• RFC 1321 compliant
• Suitable for data authentication applications
• Fully synchronous design
• Available as fully functional and synthesizable VHDL or Verilog soft-core
• Test benches provided

Symbol Diagram

Block Diagram

Functional Description

Timing diagram 1 below shows the first message block of sixteen words being clocked into the core. The INIT signal is asserted at the start of each message. The MD5 core is ready to accept data when REQ is asserted.

Each 32-bit word is clocked into the core on the rising edge of CLK when ACK is asserted. After a block of 16 words has been input, REQ is deasserted as the MD5 core computes the message digest. After another 49 clock cycles, the message digest for that 16 word block is computed and REQ is asserted again to indicate that more words can be clocked in.

Timing diagram 1 for first message block input

The standard specifies that the maximum number of bits in the message is 264 - 1. Therefore the maximum number of 32-bit words that can be clocked in is 259 - 1. The core can cope with any number of words up to 259 - 1 being input.

Timing diagram 2 below shows the last message block being clocked into the core. The LAST signal is asserted when clocking in the last word. At least one pad, and two length words need to be added to the end of the message as part of the MD5 calculation.

Note that the BYTE signal is considered valid and sampled by the core when the LAST signal is high. This signal is used by the core to determine how many bytes in the last word are part of the input data. See the signal list to see how the core interprets this signal.

If the total number of input words plus three is not a multiple of 16, additional pad bytes are added by the core to calculate the message digest as specified in the standard.

The two length words that contain the bit-length of the original message are also added by the core. Note the three clock cycle delay for adding the pad and length words.

The 160-bit message digest is output on A, B, C, D when READY is asserted.

Timing diagram 2 showing last message block input.

The core can be asynchronously reset by lowering the RSTN input port. The clock enable signal is asserted high for normal operation. Registers are not updated when EN is forced to 0.

Implementation Results

MD5 reference designs have been evaluated in a variety of technologies.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Export Permits

This core is approved for export to Australia and the United States for military applications, and to all other countries for non-military applications, except for the following:

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the MD5 technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide