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DES Cryptoprocessor Core

Description | Applications | Features | Symbol Diagram | Block Diagram | Functional Description | Implementation Results | Support | Verification | Export Permits | Deliverables

The DES core is a fully compliant implementation of the DES encryption algorithm, suitable for a variety of applications. It supports both encryption and decryption, ECB, CBC and Triple DES versions are available. The core employs a fully synchronous design and provides a low gate count.

Applications

You can use the DES in a variety of applications, including:

• Electronic financial transactions
• Secure communications
• Secure video surveillance systems
• Encrypted data storage

Features

• NIST certified 56-bit DES implementation
• Both encryption and decryption supported
• Encryption and decryption performed in 16 clock cycles
• No dead cycles for key loading or mode switching
• Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), CFB and OFB implementations
• Triple DES implementations
• Sustained bit rate is 4 x clock speed
• High clock speed and low gate count achieved
• Suitable for data security applications
• Fully synchronous design
• Available as fully functional and synthesizable VHDL or Verilog soft-core
• Test benches provided
  

Symbol Diagram

Block Diagram

Functional Description

The DES is a block cipher that encrypts and decrypts data in 64-bit blocks using a 56-bit key. It is partitioned into modules as shown in the block diagram and described below. After an initial permutation, the input data is split into two 32-bit words, left and right. This is followed by 16 rounds of identical operations.

The right word is processed with an expansion permutation and XORed with the processed key. This is followed by the S boxes substitution. The output of the S boxes is permuted and then XORed with the left word.

The result is used to update the right word register at the end of each round. Also, the previous right word is stored in the left word register. The processed key changes at each round as well, thanks to shifts and permutation operations.

At the end of the 16 rounds the left and right words are reassembled together and passed through the inverse of the initial permutation.

Encryption or decryption behavior is selected by the E_D signal. If this signal is high the core performs encryption, otherwise decryption is performed.

Rising the input on the GO port triggers the beginning of a cryptographic operation on the data DIN using the KEY as key.

Only 56 of the 64 bits of the KEY input port are considered by the core, according to the DES algorithm. A bit every eight is ignored from the KEY input.

Implementation Results

DES reference designs have been evaluated in a variety of technologies.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Export Permits

This core is approved for export to Australia and the United States for military applications, and to all other countries for non-military applications, except for the following:

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the DES technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide