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AES Advanced Encryption Standard Core

Description | Features | Applications | Block Diagram | Implementation | Export Permits | Deliverables

The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for128-, 192-, and 256-bit key lengths.

Different versions provide the best speed/area results for specific applications. Various cipher modes can be supported (ECB, CBC, OFB, CFB, CTR, CCM), different datapath widths are possible, and smaller or faster architectures are available. The core works with a pre-expanded key, or with optional key expansion logic.

The fully synchronous design is available in source or netlist forms.

Features

• Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
• Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
• Processes 128-bit data in 32-bit blocks
• Employs user-programmable key size of 128, 192 or 256 bits
• Smallest version supports a single block cipher mode, Electronic Codebook (ECB); these modes can be added as needed: Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB), Counter (CTR) and Counter with CBC-MAC (CCM)
• Works with a pre-expended key or can integrate the optional key expansion function
• Simple, fully synchronous, reusable design
• Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
• Complete deliverables include test benches

Applications

• Protected network routers
• Electronic financial transactions
• Secure wireless communications
• Secure video surveillance systems
• Encrypted data storage

Block Diagram

Implementation Results

Device Utilization and Performance

Representative performance figures are shown here.

Representative ASIC Performance Figures

Export Permits

This core is approved for export to Australia and the United States for military applications, and to all other countries for non-military applications, except for the following:

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the AES technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide