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AES_E Advanced Encryption Standard

Encoding Core

The AES_E core implements Rijndael encoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for128-, 192-, and 256-bit key lengths.

Different versions provide the best speed/area results for specific applications. Various cipher modes can be supported (ECB, CBC, OFB, CFB, CTR), different datapath widths are possible, and smaller or faster architectures are available. The core works with a pre-expanded key, or with optional key expansion logic.

The fully synchronous design is available in source or netlist forms.

Features

Encrypts using the AES Rijndael Block Cipher Algorithm
Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
Processes 128-bit data in 32-bit blocks
Employs user-programmable key size of 128, 192 or 256 bits
Smallest version supports a single block cipher mode, Electronic Codebook (ECB); these modes can be added as needed: Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB) and Counter (CTR)
Works with a pre-expended key or can integrate the optional key expansion function
Simple, fully synchronous, reusable design
Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
Complete deliverables include test benches

Applications

Protected network routers
Electronic financial transactions
Secure wireless communications
Secure video surveillance systems
Encrypted data storage

Block Diagram

Implementation Results

Device Utilization and Performance

Representative performance figures for 32-bit datapath ECB mode with optimization for speed are shown in Table 3.

Core	Technology	Area	Speed	Throughput with 128-bit key
AES_E	0.18 u	4.9 Kgates	384 MHz	~1.11 Gbit/s
AES_E	0.25 u	6.0 Kgates	294 MHz	~855 Mbit/s
KEXP_E	0.18 u	5.9 Kgates	400 MHz	~1.16 Gbit/s
KEXP_E	0.25 u	5.7 Kgates	315 MHz	~913 Mbit/s

Table 3 – Representative ASIC Performance Figures

Throughput Comparisons

The throughput of the AES_E core is influenced by the width of the datapath as well as the clock frequency. Clock frequencies can be expected to be over 250 MHz in a 0.18 μm ASIC. The datapath width can be 32 and 128 bits. Fully pipelined designs are also available for a throughput of over 25 Gbps.

Core	Datapath Width	Approx. Area	Throughput bits/cycle	Throughput at 200 MHz
AES core without key expander	32	4 Kgates	~2.9	~580 Mbit/s
AES core without key expander	128	16 Kgates	~11.6	~2.32 Gbit/s
Key Expander core	32	5.5 Kgates	~2.9	~580 Mbit/s
Key Expander core	128	22 Kgates	~11.6	~2.32 Gbit/s

Table 4 – Representative Throughput Results

Export Permits

This core is approved for export to Australia and the United States for military applications, and to all other countries for non-military applications, except for the following:

Cuba	Iran	Iraq	Libya
North Korea	Sudan	Syria

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the AES_E technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide

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