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USBHS-OTG-SD USB2.0 On-The-Go

Controller Core

Description | Features | Applications | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables

Implements a high-speed USB port that can serve as either a host or a peripheral when connected to other USB devices.

This dual-role behavior conforms to the USB 2.0 specification and its On-The-Go Supplement. The core is designed for processing efficiency — with hardware implementing the Host Negotiation Protocol, Session Request Protocol, and other critical functions — and is competitive in both performance and area usage.

Standard USB transceivers can be used through the core’s UTMI+ interface. The core’s system connection is through a standard PVCI interface (AMBA and other standard interfaces are also available). Configurable endpoints and other USB characteristics can be customized prior to synthesis to match the core to a specific application, and the core supports USB power saving functions.

The USBHS-OTG-SD is a testable, microcode-free design developed for reuse in ASICs and FPGAs. A complete test environment helps designers verify the functioning and compliance of the core, and includes a behavioral model of the PHY software layer (a USB stimulator model) to allow easy transaction simulation.

Features

• Complies with the USB 2.0 specification and its On-The-Go supplement
• Supports one Low-Speed, Full-Speed, or High-Speed peripheral device in Host mode
• Supports Full-Speed and High-Speed data transfer in Peripheral mode
• Provides hardware-based support for the Host Negotiation Protocol (HNP) and the Session Request Protocol (SRP)
• Includes endpoint 0 for USB control transfers
• Configurable for up to 15 IN and 15 OUT additional endpoints, each with:
  • Configurable and programmable size
  • Configurable and programmable single, double, triple or quad buffering
  • Programmable type (bulk, ISO, interrupt)
• UTMI+ (USB 2.0 Transceiver Macrocell Interface Plus) for use with any compliant transceiver macrocell
• 32-bit Peripheral Virtual Component Interface (PVCI) to microprocessor (other standard interfaces available)
• Offers direct access to the endpoint buffers via a configurable 8/16/32 -bit slave FIFO inter-face
• Ready for an external DMA module
• Synchronous dual-port RAM interface for endpoint buffers
• Suspend and resume power management functions
• Remote wake-up function
• Strictly synchronous design with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.

Applications

Serves as a USB 2.0 host or a peripheral, allowing the direct connection of digital products without the need for a computer host. Examples include:

• Connecting a digital camera directly to a printer for prints or to a cellular phone for Internet photo sharing.
• Connecting a digital music player to a CD player to download songs, to a set of speakers to play them, and to a disk burner to archive custom playlists.
• Connecting a PDA to a flash memory drive for backing up data, to a logic analyzer for transferring lab results, or to another PDA for file sharing.

Block Diagram

Functional Description

The USBHS-OTG-SD core is partitioned into modules as shown in the block diagram and described below.

UTMI+ Interface

The core requires an external transceiver that is compatible with the USB 2.0 UTMI+ specification (Philips USB 2.0 Transceiver Macrocell Interface Plus, version 1.0).

OTG Controller

Supports the tasks specified in the OTG Supplement. It in-cludes hardware implementations of the Host Negotiation Protocol (HNP) and the Session Request Protocol (SRP), and special function registers for their control.

This block manages the upstream and downstream activity on the USB OTG port, and chooses between them. The de-fault operation mode is determined by which end of the USB OTG cable the user has inserted into the port: one end makes the core operate as a host, the other end a peripheral.

Host Controller

Functions when the core operates as a host, with the main tasks of generating suspend/resume and USB reset sig-nals, generating Start of Frame (SOF) tokens, managing USB data transactions, and generating host interrupts. It includes a hardware Host Transaction Scheduler and a frame generator.

Device (Peripheral Mode) Controller

Supports all types of USB 2.0 data transfers in peripheral mode, and performs additional standard operations such as receiving SOF tokens, detecting suspend/resume signals, and controlling the remote wakeup function.

Endpoints Logic Blocks

Includes endpoint 0 to support USB control requests, and up to 15 additional endpoints for custom requests. Supports all four types of USB data transfers:

• Control transfer – interactions with standard endpoint 0
• Interrupt transfer – data transfer from an interrupt-driven device to host
• Bulk transfer – transfer for a large amount of data
• Isochronous transfer – for applications requiring constant data transfer rates

Generates read/write signals for two dual synchronous RAM blocks, one for OUT and one for IN endpoints. The number, size, and buffering of up to 15 IN and 15 OUT endpoints can be configured before synthesis.

SFRS

Contains a set of Special Function Registers that control the core’s operation.

Application Interface

Contains an interrupt controller that generates interrupt signals for microprocessor, the standard PVCI microprocessor interface, and a slave FIFO interface that provides direct access to the endpoint buffers.

Implementation Results

USBHS-OTG-SD reference designs have been evaluated in a variety of technologies. The following are sample results using Area optimized for speed, and configured for operation with 1 IN and 1 OUT quad-buffered endpoints.

Support

The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements, and has been implemented and tested in a demonstration application.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• An example chip implementation
• Extensive HDL Testbench including external endpoint buffers, a bus/behavioral model USB stimulator (PHY), and a clock generator
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide