The CUSB2 core implements a complete high/full-speed (480/12 Mbps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s microprocessor on the other. It is user-configurable for up to 15 IN and OUT endpoints, and includes power management and remote wake-up functions.
An integrated configuration/enumeration FSM and support for the Philips ISP1501 transceiver are options.
Designed for easy reuse, a typical minimum configuration of the core requires 8700 ASIC gates.
Features
Full compliance with the USB 2.0 specification
Control endpoint 0 — fixed 64 Bytes size
Configurable for up to 15 IN and 15 OUT endpoints
Configurable/programmable number and size of endpoints
Configurable/programmable single, double, triple or quad buffering
Programmable type of endpoints
UTMI Transceiver Macrocell Interface
Configurable 8-, 16-, or 32-bit microprocessor interface
Easy integration with a wide range microprocessors and bus architectures
Interrupt request signals for application microprocessor
Interrupt vector for autovectored interrupts
Direct access to the endpoints buffers via configurable 8-, 16-, or 32-bit Slave FIFO interface
Ready for external DMA module
Synchronous RAM interface for FIFOs
Suspend and resume power management functions
Remote Wake-Up function
Optional configuration/Enumeration FSM can be added before delivery
Support for USB standard requests (described in Chapter 9 of the USB Specification)
Interface for asynchronous ROM with the USB function descriptors
Optional support for Philips ISP1501 USB2.0 Transceiver can be added before delivery
Applications
Embedded microcontroller systems
Communication systems
Block Diagram
Implementation Results
Reference designs show that a typical configuration of the CUSB2 core for a 16-bit USB 2.0 transceiver data bus (UTMI clock = 30 Mhz), 32-bit CPU and Slave FIFO buses uses just 13,800 gates in a TSMC 0.13 um ASIC. (This typical configuration includes a configuration FSM, endpoint 0 and two additional single buffered, 1024-byte endpoints, IN and OUT, as might be used for a USB mass storage device.)
