The SPI_Slave core implements a slave for the Serial Protocol Interface (SPI) protocol. The core can be programmed to run either in pure SPI mode, where bi-directional 1-byte transactions are implemented, or in extended SPI mode, where read or write transactions of 14-bit address/32-bit data are implemented.
Developed for easy reuse with ASICs or FPGAs, the core requires just 1000 ASIC gates.
Symbol
Features
SPI-Slave operation
”Pure SPI” run-time mode:
Duplex communication
Byte transactions
USART-like internal interface
”Extended SPI” run-time mode (over-SPI protocol):
Read or write transactions with 14bits address field and 32bits data field
RAM-like internal interface
Applications
The core is suitable for implementing serial interfaces in a wide range of applications, including:
Embedded microprocessor boards and SOCs
Consumer and professional audio/video
Home and automotive radio
Block Diagram
Implementation Results
The SPI_SLAVE reference designs have been evaluated in a variety of technologies.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide
