Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.0a, including the Transaction, Data Link, and Physical protocol layers.
The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications—x1 (single lane) and x4 (four lane), with x8 (eight lane) under development—and offers bi-directional data rates from 250MB/s (x1) to 1GB/s (x4). It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redun-dancy check, and power management features. Multi-lane versions of the core support lane reversal and polarity inversion.
The synchronous, latch-free core design has an application interface layer that imple-ments an asynchronous clock boundary between the core logic and the user’s application. Standard bus interfaces such as Wishbone or AMBA are available, as is a generic interface for use with any system. The external connection interface conforms to the Intel PIPE specification, ensuring compatibility with any 16-bit PIPE-compliant PHY.
The core was rigorously verified for compliance with the PCI Express specification us-ing Denali’s PureSpec PCIe verification IP and PureSuite compliance test suite.
Features
Compliant with PCI Express Base Specification 1.0a
Implements Transaction, Data Link, and Physical protocol layers in hardware
Supports x1 and x4 link widths
Offers a data rate of 2.5 Gbps per lane
Supports up to eight Virtual Channels
Supports lane reversal and polarity inversion
PCI Configuration space type 0 header
MSI capability support
End-to-end cyclic redundancy code (ECRC) generation and checking support
Advanced Error Reporting capability support
Configurable TLP data payload size, from 128B to 4kB
Configurable size for the Transmit Retry and Receive data buffers
Modular architecture
Synchronous design
64-bit internal datapath at 125MHz
Support for asynchronous application and core clocks
Easy system integration through generic or industry standard bus interfaces (e.g., Wishbone, AMBA)
Conforms to standard PIPE interface for compatibility with any 16-bit PIPE-compliant PHY
Applications
PCI Express is rapidly being adopted for a variety of interconnection applications, including:
Network servers
Graphics and multimedia
Communications and mobile product
Industrial, automotive, and other embedded systems
Block Diagram
Functional Description
The core is divided into four modules responsible for the Configuration Space, Transaction Layer, Data Link Layer, and Physical Layer MAC.
Configuration Space
Provides a Configuration space register file type 0. In addition to the mandatory functions, numerous extended capabilities are also supported.
Transaction Layer module
Responsible for the assembly and disassembly of transaction layer packets. The transaction layer supports four address spaces: Configuration space, Memory space, I/O space and Message Space. Power management services are supported.
Data Link Layer module
Responsible for link management, data protection and integrity checking, retry and power management services.
Physical Layer MAC module
Implements the logical subblock of the physical layer. The module is responsible for link training and status monitoring, link width negotiation, lane order negotiation, lane polarity reversal control and power management implementation.
Implementation Results
PCIe-EP reference designs are being evaluated in a variety of technologies; the results from several implementations of the core are shown below (at the required frequency of 125 MHz and with a single VC and no ECRC).
Link Width
Technology
Approx. Area
x1
TSMC 0.13 μm
62,941 gates
x1
TSMC 0.18μm
67,612 gates
x4
TSMC 0.13 μm
78,990 gates
x4
TSMC 0.13 μm
84,251 gates
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements, and has been thor-oughly tested for specification compliance using Denali’s PureSpec PCIe verification IP and PureSuite compliance test suite.
Deliverables
The core is available in ASIC (synthesizable) or FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:
HDL RTL source
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis script
Comprehensive user documentation, including detailed specifications and a system integration guide
