MAC 10/100 Ethernet Media Access
Controller Core
Description | Features | Applications | Symbol | Block Diagram | Functional Description | Implementation Results | Support | Verification | Deliverables
The MAC is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over Ethernet.
Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers the MAC operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from an external host and provides resolution in case of latency of an external bus.
Special care was taken to facilitate easy integration of the MAC with the other Virtual Components (VCs) in the Systems on Chip (SoC). The core has a generic host side interface for connecting with external CPUs or with standard bus controllers such as PCI. This host interface can be configured to work with 8, 16, or 32 data bus lengths with big or little endian byte ordering and is compatible with most modern virtual component interfaces.
Features
- Network interface features
- Supports 10/100Mb/s data transfer rates
- Media Independent Interface (MII)
- Data link layer functionality
- Meets the IEEE 802.3 CSMA/CD standard
- Full or half duplex operation
- Flexible address filtering
- External RAM for storing MAC addresses
- Up to 16 physical addresses
- 512 bit hash table for multicast addresses
- Control and status registers
- Configurable 8/16/32 bit data bus length
- Single interrupt line
- Interrupt mitigation control mechanism
- DMA controller
- Configurable 8/16/32 bit data bus length
- Configurable address bus length
- Big or little endian data byte ordering
- Scatter/gather capabilities
- Programmable burst length
- Intelligent arbitration between transmit and receive processes
- Descriptor/buffer architecture for data storage
- Descriptor "ring" or "chain" structures
- Automatic descriptor list pooling
- Transmit/Receive dual port RAM interfaces
- Operates as internal configurable FIFOs
- Programmable threshold levels
- "Store and forward" functionality
Applications
The MAC core can be utilized for a variety of serial communication applications including:
- Network Interface Cards (NICs)
- Routers, switching hubs
- Systems On Chip (SoCs) Applications
Symbol Diagram
Block Diagram
Functional Description
The MAC core consist of the following components:
TC - Transmit Controller
The transmit controller implements the 802.3 transmit operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The transmit controller operates synchronously with the clkt clock from the MII interface.
BD - Backoff/Deferring
The backoff/deferring controller implements the 802.3 half duplex operation. It operates synchronously with the clkt clock from the MII interface. The backoff/deferring controller can be removed for lower gate-count if the half duplex operation is not required.
RC - Receive Controller
The receive controller implements the 802.3 receive operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The receive controller operates synchronously with the clkr clock from the MII interface.
TFIFO - Transmit FIFO
The transmit FIFO is used for buffering data prepared for transmission by the MAC. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The TFIFODEPTH parameter defines the total FIFO size. The TCDEPTH parameter defines the maximum number of frames that can reside in the transmit FIFO at the moment. The transmit FIFO controller operates synchronously with the clkdma clock from the host Data interface.
RFIFO - Receive FIFO
The receive FIFO is used for buffering data received by the MAC. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The RFIFODEPTH parameter defines the total FIFO size. The RCDEPTH parameter defines the maximum number of frames that can reside in the receive FIFO at the moment. The receive FIFO controller operates synchronously with the clkdma clock from the host Data interface.
TLSM - Transmit linked List State Machine
The transmit linked list state machine implements the descriptor/buffer architecture of the MAC. It manages the transmit descriptor list, and fetches the data prepared for transmission from the data buffers into the transmit FIFO. The transmit linked list state machine controller operates synchronously with the clkdma clock from the host Data interface.
RLSM - Receive linked List State Machine
The receive linked list state machine implements the descriptor/buffer architecture of the MAC. It manages the receive descriptor list, and moves the data the receive FIFO into the data buffers. The receive linked list state machine controller operates synchronously with the clkdma clock from the host Data interface.
DMA - Direct Memory Access controller
The direct memory access controller implements the host Data interface. It services both the receive and the transmit channels. The direct memory access controller operates synchronously with the clkdma clock from the host Data interface.
CSR - Control and Status Registers
The CSR component is used to control the MAC operation by the host. It implements the register set, the interrupt controller, and the power management functionality of the MAC. It also provides an interface for the host. The CSR component operates synchronously with the clkcsr clock from the host CSR interface.
RSTC - Reset Controller
The reset controller is used to reset for all components of the MAC. It generates reset signal synchronous to all clock domains in the design from the single external reset line.
External components
There are three external components required for proper operation of the MAC core:
- Receive data RAM - synchronous dual port RAM working as receive FIFO.
- Transmit data RAM - synchronous dual port RAM working as transmit FIFO.
- Address RAM - synchronous dual port RAM working as MAC addresses memory.
Implementation Results
MAC reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including:
- The MAC core
- On chip dual port RAMs
- Bus/behavioral models of host, shared RAM and PHY devices
- Clock generator
- Processes that compare your simulation results with the expected results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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