The C139A core implements a link layer controller for the high-speed, high-bandwidth serial bus known commercially as FireWire(TM) and i.Link(TM).
The core conforms to the IEEE 1394-1995 and 1394a-2000 specifications. It is similar to the popular Texas Instruments TSB12LV32 General Purpose Link Layer Controller, but includes a 32-bit APB interface for easy connection with an AMBA(TM) bus host system. (AHB and other standard interfaces are also available.)
The C1394A can interface with any 1394-compliant physical layer (PHY) device, and includes easy-to-apply C-language software functions for all basic operations (options provide serial bus management and the transaction layer). It is FPGA-proven and has been exercised in a FireWire video camera demonstration system. ASIC results show it to require less than 39,000 gates.
The C1394A is a testable, microcode-free design developed for reuse in ASICs and FPGAs. It is fully synchronous and has no internal three-state buses. A complete verification environment helps designers verify the functioning and compliance of the core, and additional aids for system-on-chip simulation are available.
Features
Conforms to and implements all functionality of the IEEE 1394-1995 and IEEE 1394a-2000 standards
Based on Texas Instruments TSB12LV32 General Purpose Link Layer controller
Supports device data transmission of 400, 200 and 100 Mbps
Includes 32-bit AMBA APB Slave microprocessor interface (other standard interfaces available)
Fast, direct, 16-bit Data Mover interface supervises data flow to and from the external source
Integrated receive and transmit FIFOs are configurable in size
Validates data with 32-bit CRC generation for transmission and 32-bit CRC checking on recep-tion
Capable of Bus Manager, Isochronous Resource Manager and Cycle Master modes
Able to receive all incoming isochronous traffic, and supports hardware filtering/acceptance for up to two (more available upon request)
Supports IEEE 1394 acceleration enhancement methods and the selective enabling/disabling of IEEE 1394a functions
Uses Annex J standard to interface with any compliant PHY
Dedicated software functions support all basic operations
Additional software functions available as extra options for IEEE-1394a compliant Transaction Layer and Serial Bus Management (SBM)
Debug feature introduces CRC errors during transmission
Optional System-On-Chip simulation support provides aworking physical layer and emulates traffic and other nodes on the bus
FPGA-proven, and offering competitive implementation results, e.g., 38,800 ASIC gates and 111 MHz host frequency
Applications
System integration is straightforward, as the core readily interfaces with any AMBA APB compliant host processor for control and to any 1394-1995 or 1394a-2000 compliant physical level (PHY) device for connection to a cable.
The 1394 bus facilitates the convergence of computers, peripherals, and consumer products. Typical applications include camcorders, televisions, digital cameras, external hard drives, scanners, and printers.
Symbol
Block
Implementation Results
Technology
Approx. Area
Frequency
(APB clock)
ASIC
UMC 0.18μ process
38,834 gates
111 MHz
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
An example chip implementation, which uses the C1394A in a sample system and shows how to build and connect external logic and tri-state buffers
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility
Synthesis (soft) or place and route (firm) script
Comprehensive user documentation, including detailed specifications and a system integration guide
