I2CS Philips Serial Bus Interface Slave
Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Implementation Results | Support | Verification | Deliverables
The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2cssta) reflects the status of I2CS Bus Controller and the I2C bus.
Developed for easy reuse with ASICs or FPGAs, the core requires under 900 ASIC gates.
Features
- Uses two wires to transfer information between devices
- Serial Clock Line SCL (SCL)
- Serial Data Line (SDA).
- Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
- Slave Receiver Mode - Serial data and the serial clock are received through SDA and SCL
- Slave Transmitter Mode - Serial data is transmitted via SDA while the serial clock is input through SCL
- Bi-directional data transfer
- Own address and General Call address detection
- 7 bit addressing format
- Fixed data width of 8 bits
- Data transfer in multiples of bytes
- One-byte write and read buffer
- Strictly synchronous design with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward
Applications
The I2CS can be utilized for a variety of serial interface applications.
Symbol Diagram
Block Diagram
Implementation Results
The I2CS is designed to run at frequencies of up to 200 MHz on a typical 0.5-micron process and it uses less than 900 gates depending on the technology. The I2CS is a technology independent design that can be implemented in a variety of process technologies.
ASIC Technology |
Area |
Performance |
ASIC 0.5-micron |
<900 gates |
200 MHz |
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The I2CS core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Philips 80C552 chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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