I2C-HS Master/Slave Bus Controller Core
Description | Features | Applications | Symbol Diagram | Block Diagram | Perfomance | Implementation Results | Support | Verification | Deliverables
The I2C-HS Bus Controller core provides a serial interface that meets the Philips I2C bus specification version 2.1. It is compliant with the PVCI (Peripheral Virtual Component Interface) standard which is an open standard for SoC On-Chip Bus.
The I2C-HS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
Features
- The I2C Bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line)
- Compliant to version 2.1 of the I2C Bus standard
- PVCI standard compliant (OCB 2 2.0)
- Data transfers up to 100 Kbps in standard mode, up to 400 Kbps in fast-mode, and up to 3.4 Mbps in high-speed mode
- Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock
- Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock
- Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
- Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
- Mixed-speed bus system configuration support
- Multimaster Mode
Applications
The I2C-HS can be utilized for a variety of serial interface applications.
Symbol Diagram
Block Diagram
Performance
The I2C-HS is designed to run at frequencies of up to 160 MHz on a typical 0.18-micron process, and it uses less than 2,000 gates depending on the technology. The I2C-HS is a technology-independent design that can be implemented in a variety of process technologies.
Implementation Results
I2C-HS reference designs have been evaluated in a variety of technologies.
Support
The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The I2C-HS core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Atmel 89C51IC2 and Texas Instruments TMP100chip, and the results compared with the core’s simulation outputs.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench that instantiates:
- The I2C-HS core
- Clock generator
- Bus/behavioral model of the I2C-HS
- Bus/behavioral model for the 8051 Host
- Process that compares the simulation results with the expected results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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